1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/arch/arm/mach-mmp/mmp2.c 4 * 5 * code name MMP2 6 * 7 * Copyright (C) 2009 Marvell International Ltd. 8 */ 9#include <linux/clk/mmp.h> 10#include <linux/module.h> 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/io.h> 14#include <linux/irq.h> 15#include <linux/irqchip/mmp.h> 16#include <linux/platform_device.h> 17 18#include <asm/hardware/cache-tauros2.h> 19 20#include <asm/mach/time.h> 21#include "addr-map.h" 22#include "regs-apbc.h" 23#include <linux/soc/mmp/cputype.h> 24#include "irqs.h" 25#include "mfp.h" 26#include "devices.h" 27#include "mmp2.h" 28#include "pm-mmp2.h" 29 30#include "common.h" 31 32#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 33 34static struct mfp_addr_map mmp2_addr_map[] __initdata = { 35 36 MFP_ADDR_X(GPIO0, GPIO58, 0x54), 37 MFP_ADDR_X(GPIO59, GPIO73, 0x280), 38 MFP_ADDR_X(GPIO74, GPIO101, 0x170), 39 40 MFP_ADDR(GPIO102, 0x0), 41 MFP_ADDR(GPIO103, 0x4), 42 MFP_ADDR(GPIO104, 0x1fc), 43 MFP_ADDR(GPIO105, 0x1f8), 44 MFP_ADDR(GPIO106, 0x1f4), 45 MFP_ADDR(GPIO107, 0x1f0), 46 MFP_ADDR(GPIO108, 0x21c), 47 MFP_ADDR(GPIO109, 0x218), 48 MFP_ADDR(GPIO110, 0x214), 49 MFP_ADDR(GPIO111, 0x200), 50 MFP_ADDR(GPIO112, 0x244), 51 MFP_ADDR(GPIO113, 0x25c), 52 MFP_ADDR(GPIO114, 0x164), 53 MFP_ADDR_X(GPIO115, GPIO122, 0x260), 54 55 MFP_ADDR(GPIO123, 0x148), 56 MFP_ADDR_X(GPIO124, GPIO141, 0xc), 57 58 MFP_ADDR(GPIO142, 0x8), 59 MFP_ADDR_X(GPIO143, GPIO151, 0x220), 60 MFP_ADDR_X(GPIO152, GPIO153, 0x248), 61 MFP_ADDR_X(GPIO154, GPIO155, 0x254), 62 MFP_ADDR_X(GPIO156, GPIO159, 0x14c), 63 64 MFP_ADDR(GPIO160, 0x250), 65 MFP_ADDR(GPIO161, 0x210), 66 MFP_ADDR(GPIO162, 0x20c), 67 MFP_ADDR(GPIO163, 0x208), 68 MFP_ADDR(GPIO164, 0x204), 69 MFP_ADDR(GPIO165, 0x1ec), 70 MFP_ADDR(GPIO166, 0x1e8), 71 MFP_ADDR(GPIO167, 0x1e4), 72 MFP_ADDR(GPIO168, 0x1e0), 73 74 MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140), 75 MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc), 76 77 MFP_ADDR(PMIC_INT, 0x2c4), 78 MFP_ADDR(CLK_REQ, 0x160), 79 80 MFP_ADDR_END, 81}; 82 83void mmp2_clear_pmic_int(void) 84{ 85 void __iomem *mfpr_pmic; 86 unsigned long data; 87 88 mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; 89 data = __raw_readl(mfpr_pmic); 90 __raw_writel(data | (1 << 6), mfpr_pmic); 91 __raw_writel(data, mfpr_pmic); 92} 93 94void __init mmp2_init_irq(void) 95{ 96 mmp2_init_icu(); 97#ifdef CONFIG_PM 98 icu_irq_chip.irq_set_wake = mmp2_set_wake; 99#endif 100} 101 102static int __init mmp2_init(void) 103{ 104 if (cpu_is_mmp2()) { 105#ifdef CONFIG_CACHE_TAUROS2 106 tauros2_init(0); 107#endif 108 mfp_init_base(MFPR_VIRT_BASE); 109 mfp_init_addr(mmp2_addr_map); 110 mmp2_clk_init(APB_PHYS_BASE + 0x50000, 111 AXI_PHYS_BASE + 0x82800, 112 APB_PHYS_BASE + 0x15000); 113 } 114 115 return 0; 116} 117postcore_initcall(mmp2_init); 118 119#define APBC_TIMERS APBC_REG(0x024) 120 121void __init mmp2_timer_init(void) 122{ 123 unsigned long clk_rst; 124 125 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); 126 127 /* 128 * enable bus/functional clock, enable 6.5MHz (divider 4), 129 * release reset 130 */ 131 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); 132 __raw_writel(clk_rst, APBC_TIMERS); 133 134 mmp_timer_init(IRQ_MMP2_TIMER1, 6500000); 135} 136 137/* on-chip devices */ 138MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); 139MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); 140MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); 141MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); 142MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); 143MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); 144MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); 145MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); 146MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); 147MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); 148MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); 149MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120); 150MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120); 151MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120); 152MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120); 153MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000); 154/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */ 155MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000); 156 157struct resource mmp2_resource_gpio[] = { 158 { 159 .start = 0xd4019000, 160 .end = 0xd4019fff, 161 .flags = IORESOURCE_MEM, 162 }, { 163 .start = IRQ_MMP2_GPIO, 164 .end = IRQ_MMP2_GPIO, 165 .name = "gpio_mux", 166 .flags = IORESOURCE_IRQ, 167 }, 168}; 169 170struct platform_device mmp2_device_gpio = { 171 .name = "mmp2-gpio", 172 .id = -1, 173 .num_resources = ARRAY_SIZE(mmp2_resource_gpio), 174 .resource = mmp2_resource_gpio, 175}; 176