1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arch/mach-ixp4xx/vulcan-pci.c
4 *
5 * Vulcan board-level PCI initialization
6 *
7 * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
8 *
9 * based on ixdp425-pci.c:
10 *	Copyright (C) 2002 Intel Corporation.
11 *	Copyright (C) 2003-2004 MontaVista Software, Inc.
12 */
13
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <asm/mach/pci.h>
18#include <asm/mach-types.h>
19
20#include "irqs.h"
21
22/* PCI controller GPIO to IRQ pin mappings */
23#define INTA	2
24#define INTB	3
25
26void __init vulcan_pci_preinit(void)
27{
28#ifndef CONFIG_IXP4XX_INDIRECT_PCI
29	/*
30	 * Cardbus bridge wants way more than the SoC can actually offer,
31	 * and leaves the whole PCI bus in a mess. Artificially limit it
32	 * to 8MB per region. Of course indirect mode doesn't have this
33	 * limitation...
34	 */
35	pci_cardbus_mem_size = SZ_8M;
36	pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
37		(int)(pci_cardbus_mem_size >> 20));
38#endif
39	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
40	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
41	ixp4xx_pci_preinit();
42}
43
44static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
45{
46	if (slot == 1)
47		return IXP4XX_GPIO_IRQ(INTA);
48
49	if (slot == 2)
50		return IXP4XX_GPIO_IRQ(INTB);
51
52	return -1;
53}
54
55struct hw_pci vulcan_pci __initdata = {
56	.nr_controllers	= 1,
57	.ops		= &ixp4xx_ops,
58	.preinit	= vulcan_pci_preinit,
59	.setup		= ixp4xx_setup,
60	.map_irq	= vulcan_map_irq,
61};
62
63int __init vulcan_pci_init(void)
64{
65	if (machine_is_arcom_vulcan())
66		pci_common_init(&vulcan_pci);
67	return 0;
68}
69
70subsys_initcall(vulcan_pci_init);
71