18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * arch/arm/mach-ixp4xx/miccpt-pci.c
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * MICCPT board-level PCI initialization
68c2ecf20Sopenharmony_ci *
78c2ecf20Sopenharmony_ci * Copyright (C) 2002 Intel Corporation.
88c2ecf20Sopenharmony_ci * Copyright (C) 2003-2004 MontaVista Software, Inc.
98c2ecf20Sopenharmony_ci * Copyright (C) 2006 OMICRON electronics GmbH
108c2ecf20Sopenharmony_ci *
118c2ecf20Sopenharmony_ci * Author: Michael Jochum <michael.jochum@omicron.at>
128c2ecf20Sopenharmony_ci */
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_ci#include <linux/kernel.h>
158c2ecf20Sopenharmony_ci#include <linux/pci.h>
168c2ecf20Sopenharmony_ci#include <linux/init.h>
178c2ecf20Sopenharmony_ci#include <linux/delay.h>
188c2ecf20Sopenharmony_ci#include <linux/irq.h>
198c2ecf20Sopenharmony_ci#include <asm/mach/pci.h>
208c2ecf20Sopenharmony_ci#include <asm/irq.h>
218c2ecf20Sopenharmony_ci#include <mach/hardware.h>
228c2ecf20Sopenharmony_ci#include <asm/mach-types.h>
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_ci#include "irqs.h"
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci#define MAX_DEV		4
278c2ecf20Sopenharmony_ci#define IRQ_LINES	4
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci/* PCI controller GPIO to IRQ pin mappings */
308c2ecf20Sopenharmony_ci#define INTA		1
318c2ecf20Sopenharmony_ci#define INTB		2
328c2ecf20Sopenharmony_ci#define INTC		3
338c2ecf20Sopenharmony_ci#define INTD		4
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_civoid __init miccpt_pci_preinit(void)
378c2ecf20Sopenharmony_ci{
388c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
398c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
408c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
418c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
428c2ecf20Sopenharmony_ci	ixp4xx_pci_preinit();
438c2ecf20Sopenharmony_ci}
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_cistatic int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
468c2ecf20Sopenharmony_ci{
478c2ecf20Sopenharmony_ci	static int pci_irq_table[IRQ_LINES] = {
488c2ecf20Sopenharmony_ci		IXP4XX_GPIO_IRQ(INTA),
498c2ecf20Sopenharmony_ci		IXP4XX_GPIO_IRQ(INTB),
508c2ecf20Sopenharmony_ci		IXP4XX_GPIO_IRQ(INTC),
518c2ecf20Sopenharmony_ci		IXP4XX_GPIO_IRQ(INTD)
528c2ecf20Sopenharmony_ci	};
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ci	if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
558c2ecf20Sopenharmony_ci		return pci_irq_table[(slot + pin - 2) % 4];
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ci	return -1;
588c2ecf20Sopenharmony_ci}
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_cistruct hw_pci miccpt_pci __initdata = {
618c2ecf20Sopenharmony_ci	.nr_controllers = 1,
628c2ecf20Sopenharmony_ci	.ops		= &ixp4xx_ops,
638c2ecf20Sopenharmony_ci	.preinit	= miccpt_pci_preinit,
648c2ecf20Sopenharmony_ci	.setup		= ixp4xx_setup,
658c2ecf20Sopenharmony_ci	.map_irq	= miccpt_map_irq,
668c2ecf20Sopenharmony_ci};
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ciint __init miccpt_pci_init(void)
698c2ecf20Sopenharmony_ci{
708c2ecf20Sopenharmony_ci	if (machine_is_miccpt())
718c2ecf20Sopenharmony_ci		pci_common_init(&miccpt_pci);
728c2ecf20Sopenharmony_ci	return 0;
738c2ecf20Sopenharmony_ci}
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_cisubsys_initcall(miccpt_pci_init);
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