1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Goramo MultiLink router platform code
4 * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
5 */
6
7#include <linux/delay.h>
8#include <linux/gpio.h>
9#include <linux/hdlc.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/platform_data/wan_ixp4xx_hss.h>
15#include <linux/serial_8250.h>
16#include <asm/mach-types.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/flash.h>
19#include <asm/mach/pci.h>
20#include <asm/system_info.h>
21
22#include "irqs.h"
23
24#define SLOT_ETHA		0x0B	/* IDSEL = AD21 */
25#define SLOT_ETHB		0x0C	/* IDSEL = AD20 */
26#define SLOT_MPCI		0x0D	/* IDSEL = AD19 */
27#define SLOT_NEC		0x0E	/* IDSEL = AD18 */
28
29/* GPIO lines */
30#define GPIO_SCL		0
31#define GPIO_SDA		1
32#define GPIO_STR		2
33#define GPIO_IRQ_NEC		3
34#define GPIO_IRQ_ETHA		4
35#define GPIO_IRQ_ETHB		5
36#define GPIO_HSS0_DCD_N		6
37#define GPIO_HSS1_DCD_N		7
38#define GPIO_UART0_DCD		8
39#define GPIO_UART1_DCD		9
40#define GPIO_HSS0_CTS_N		10
41#define GPIO_HSS1_CTS_N		11
42#define GPIO_IRQ_MPCI		12
43#define GPIO_HSS1_RTS_N		13
44#define GPIO_HSS0_RTS_N		14
45/* GPIO15 is not connected */
46
47/* Control outputs from 74HC4094 */
48#define CONTROL_HSS0_CLK_INT	0
49#define CONTROL_HSS1_CLK_INT	1
50#define CONTROL_HSS0_DTR_N	2
51#define CONTROL_HSS1_DTR_N	3
52#define CONTROL_EXT		4
53#define CONTROL_AUTO_RESET	5
54#define CONTROL_PCI_RESET_N	6
55#define CONTROL_EEPROM_WC_N	7
56
57/* offsets from start of flash ROM = 0x50000000 */
58#define CFG_ETH0_ADDRESS	0x40 /* 6 bytes */
59#define CFG_ETH1_ADDRESS	0x46 /* 6 bytes */
60#define CFG_REV			0x4C /* u32 */
61#define CFG_SDRAM_SIZE		0x50 /* u32 */
62#define CFG_SDRAM_CONF		0x54 /* u32 */
63#define CFG_SDRAM_MODE		0x58 /* u32 */
64#define CFG_SDRAM_REFRESH	0x5C /* u32 */
65
66#define CFG_HW_BITS		0x60 /* u32 */
67#define  CFG_HW_USB_PORTS	0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
68#define  CFG_HW_HAS_PCI_SLOT	0x00000008
69#define  CFG_HW_HAS_ETH0	0x00000010
70#define  CFG_HW_HAS_ETH1	0x00000020
71#define  CFG_HW_HAS_HSS0	0x00000040
72#define  CFG_HW_HAS_HSS1	0x00000080
73#define  CFG_HW_HAS_UART0	0x00000100
74#define  CFG_HW_HAS_UART1	0x00000200
75#define  CFG_HW_HAS_EEPROM	0x00000400
76
77#define FLASH_CMD_READ_ARRAY	0xFF
78#define FLASH_CMD_READ_ID	0x90
79#define FLASH_SER_OFF		0x102 /* 0x81 in 16-bit mode */
80
81static u32 hw_bits = 0xFFFFFFFD;    /* assume all hardware present */;
82static u8 control_value;
83
84/*
85 * FIXME: this is reimplementing I2C bit-bangining. Move this
86 * over to using driver/i2c/busses/i2c-gpio.c like all other boards
87 * and register proper I2C device(s) on the bus for this. (See
88 * other IXP4xx boards for examples.)
89 */
90static void set_scl(u8 value)
91{
92	gpio_set_value(GPIO_SCL, !!value);
93	udelay(3);
94}
95
96static void set_sda(u8 value)
97{
98	gpio_set_value(GPIO_SDA, !!value);
99	udelay(3);
100}
101
102static void set_str(u8 value)
103{
104	gpio_set_value(GPIO_STR, !!value);
105	udelay(3);
106}
107
108static inline void set_control(int line, int value)
109{
110	if (value)
111		control_value |=  (1 << line);
112	else
113		control_value &= ~(1 << line);
114}
115
116
117static void output_control(void)
118{
119	int i;
120
121	gpio_direction_output(GPIO_SCL, 1);
122	gpio_direction_output(GPIO_SDA, 1);
123
124	for (i = 0; i < 8; i++) {
125		set_scl(0);
126		set_sda(control_value & (0x80 >> i)); /* MSB first */
127		set_scl(1);	/* active edge */
128	}
129
130	set_str(1);
131	set_str(0);
132
133	set_scl(0);
134	set_sda(1);		/* Be ready for START */
135	set_scl(1);
136}
137
138
139static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
140
141static int hss_set_clock(int port, unsigned int clock_type)
142{
143	int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
144
145	switch (clock_type) {
146	case CLOCK_DEFAULT:
147	case CLOCK_EXT:
148		set_control(ctrl_int, 0);
149		output_control();
150		return CLOCK_EXT;
151
152	case CLOCK_INT:
153		set_control(ctrl_int, 1);
154		output_control();
155		return CLOCK_INT;
156
157	default:
158		return -EINVAL;
159	}
160}
161
162static irqreturn_t hss_dcd_irq(int irq, void *pdev)
163{
164	int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
165	int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
166	set_carrier_cb_tab[port](pdev, !i);
167	return IRQ_HANDLED;
168}
169
170
171static int hss_open(int port, void *pdev,
172		    void (*set_carrier_cb)(void *pdev, int carrier))
173{
174	int i, irq;
175
176	if (!port)
177		irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
178	else
179		irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
180
181	i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
182	set_carrier_cb(pdev, !i);
183
184	set_carrier_cb_tab[!!port] = set_carrier_cb;
185
186	if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
187		printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
188		       irq, i);
189		return i;
190	}
191
192	set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
193	output_control();
194	gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
195	return 0;
196}
197
198static void hss_close(int port, void *pdev)
199{
200	free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
201		 IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
202	set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
203
204	set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
205	output_control();
206	gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
207}
208
209
210/* Flash memory */
211static struct flash_platform_data flash_data = {
212	.map_name	= "cfi_probe",
213	.width		= 2,
214};
215
216static struct resource flash_resource = {
217	.flags		= IORESOURCE_MEM,
218};
219
220static struct platform_device device_flash = {
221	.name		= "IXP4XX-Flash",
222	.id		= 0,
223	.dev		= { .platform_data = &flash_data },
224	.num_resources	= 1,
225	.resource	= &flash_resource,
226};
227
228/* IXP425 2 UART ports */
229static struct resource uart_resources[] = {
230	{
231		.start		= IXP4XX_UART1_BASE_PHYS,
232		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
233		.flags		= IORESOURCE_MEM,
234	},
235	{
236		.start		= IXP4XX_UART2_BASE_PHYS,
237		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
238		.flags		= IORESOURCE_MEM,
239	}
240};
241
242static struct plat_serial8250_port uart_data[] = {
243	{
244		.mapbase	= IXP4XX_UART1_BASE_PHYS,
245		.membase	= (char __iomem *)IXP4XX_UART1_BASE_VIRT +
246			REG_OFFSET,
247		.irq		= IRQ_IXP4XX_UART1,
248		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
249		.iotype		= UPIO_MEM,
250		.regshift	= 2,
251		.uartclk	= IXP4XX_UART_XTAL,
252	},
253	{
254		.mapbase	= IXP4XX_UART2_BASE_PHYS,
255		.membase	= (char __iomem *)IXP4XX_UART2_BASE_VIRT +
256			REG_OFFSET,
257		.irq		= IRQ_IXP4XX_UART2,
258		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
259		.iotype		= UPIO_MEM,
260		.regshift	= 2,
261		.uartclk	= IXP4XX_UART_XTAL,
262	},
263	{ },
264};
265
266static struct platform_device device_uarts = {
267	.name			= "serial8250",
268	.id			= PLAT8250_DEV_PLATFORM,
269	.dev.platform_data	= uart_data,
270	.num_resources		= 2,
271	.resource		= uart_resources,
272};
273
274
275/* Built-in 10/100 Ethernet MAC interfaces */
276static struct resource eth_npeb_resources[] = {
277	{
278		.start		= IXP4XX_EthB_BASE_PHYS,
279		.end		= IXP4XX_EthB_BASE_PHYS + 0x0fff,
280		.flags		= IORESOURCE_MEM,
281	},
282};
283
284static struct resource eth_npec_resources[] = {
285	{
286		.start		= IXP4XX_EthC_BASE_PHYS,
287		.end		= IXP4XX_EthC_BASE_PHYS + 0x0fff,
288		.flags		= IORESOURCE_MEM,
289	},
290};
291
292static struct eth_plat_info eth_plat[] = {
293	{
294		.phy		= 0,
295		.rxq		= 3,
296		.txreadyq	= 32,
297	}, {
298		.phy		= 1,
299		.rxq		= 4,
300		.txreadyq	= 33,
301	}
302};
303
304static struct platform_device device_eth_tab[] = {
305	{
306		.name			= "ixp4xx_eth",
307		.id			= IXP4XX_ETH_NPEB,
308		.dev.platform_data	= eth_plat,
309		.num_resources		= ARRAY_SIZE(eth_npeb_resources),
310		.resource		= eth_npeb_resources,
311	}, {
312		.name			= "ixp4xx_eth",
313		.id			= IXP4XX_ETH_NPEC,
314		.dev.platform_data	= eth_plat + 1,
315		.num_resources		= ARRAY_SIZE(eth_npec_resources),
316		.resource		= eth_npec_resources,
317	}
318};
319
320
321/* IXP425 2 synchronous serial ports */
322static struct hss_plat_info hss_plat[] = {
323	{
324		.set_clock	= hss_set_clock,
325		.open		= hss_open,
326		.close		= hss_close,
327		.txreadyq	= 34,
328	}, {
329		.set_clock	= hss_set_clock,
330		.open		= hss_open,
331		.close		= hss_close,
332		.txreadyq	= 35,
333	}
334};
335
336static struct platform_device device_hss_tab[] = {
337	{
338		.name			= "ixp4xx_hss",
339		.id			= 0,
340		.dev.platform_data	= hss_plat,
341	}, {
342		.name			= "ixp4xx_hss",
343		.id			= 1,
344		.dev.platform_data	= hss_plat + 1,
345	}
346};
347
348
349static struct platform_device *device_tab[7] __initdata = {
350	&device_flash,		/* index 0 */
351};
352
353static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
354{
355#ifdef __ARMEB__
356	return __raw_readb(flash + addr);
357#else
358	return __raw_readb(flash + (addr ^ 3));
359#endif
360}
361
362static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
363{
364#ifdef __ARMEB__
365	return __raw_readw(flash + addr);
366#else
367	return __raw_readw(flash + (addr ^ 2));
368#endif
369}
370
371static void __init gmlr_init(void)
372{
373	u8 __iomem *flash;
374	int i, devices = 1; /* flash */
375
376	ixp4xx_sys_init();
377
378	if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
379		printk(KERN_ERR "goramo-mlr: unable to access system"
380		       " configuration data\n");
381	else {
382		system_rev = __raw_readl(flash + CFG_REV);
383		hw_bits = __raw_readl(flash + CFG_HW_BITS);
384
385		for (i = 0; i < ETH_ALEN; i++) {
386			eth_plat[0].hwaddr[i] =
387				flash_readb(flash, CFG_ETH0_ADDRESS + i);
388			eth_plat[1].hwaddr[i] =
389				flash_readb(flash, CFG_ETH1_ADDRESS + i);
390		}
391
392		__raw_writew(FLASH_CMD_READ_ID, flash);
393		system_serial_high = flash_readw(flash, FLASH_SER_OFF);
394		system_serial_high <<= 16;
395		system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
396		system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
397		system_serial_low <<= 16;
398		system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
399		__raw_writew(FLASH_CMD_READ_ARRAY, flash);
400
401		iounmap(flash);
402	}
403
404	switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
405	case CFG_HW_HAS_UART0:
406		memset(&uart_data[1], 0, sizeof(uart_data[1]));
407		device_uarts.num_resources = 1;
408		break;
409
410	case CFG_HW_HAS_UART1:
411		device_uarts.dev.platform_data = &uart_data[1];
412		device_uarts.resource = &uart_resources[1];
413		device_uarts.num_resources = 1;
414		break;
415	}
416	if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
417		device_tab[devices++] = &device_uarts; /* max index 1 */
418
419	if (hw_bits & CFG_HW_HAS_ETH0)
420		device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
421	if (hw_bits & CFG_HW_HAS_ETH1)
422		device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
423
424	if (hw_bits & CFG_HW_HAS_HSS0)
425		device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
426	if (hw_bits & CFG_HW_HAS_HSS1)
427		device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
428
429	hss_plat[0].timer_freq = ixp4xx_timer_freq;
430	hss_plat[1].timer_freq = ixp4xx_timer_freq;
431
432	gpio_request(GPIO_SCL, "SCL/clock");
433	gpio_request(GPIO_SDA, "SDA/data");
434	gpio_request(GPIO_STR, "strobe");
435	gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS");
436	gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS");
437	gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD");
438	gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD");
439
440	gpio_direction_output(GPIO_SCL, 1);
441	gpio_direction_output(GPIO_SDA, 1);
442	gpio_direction_output(GPIO_STR, 0);
443	gpio_direction_output(GPIO_HSS0_RTS_N, 1);
444	gpio_direction_output(GPIO_HSS1_RTS_N, 1);
445	gpio_direction_input(GPIO_HSS0_DCD_N);
446	gpio_direction_input(GPIO_HSS1_DCD_N);
447	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
448	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
449
450	set_control(CONTROL_HSS0_DTR_N, 1);
451	set_control(CONTROL_HSS1_DTR_N, 1);
452	set_control(CONTROL_EEPROM_WC_N, 1);
453	set_control(CONTROL_PCI_RESET_N, 1);
454	output_control();
455
456	msleep(1);	      /* Wait for PCI devices to initialize */
457
458	flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
459	flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
460
461	platform_add_devices(device_tab, devices);
462}
463
464
465#ifdef CONFIG_PCI
466static void __init gmlr_pci_preinit(void)
467{
468	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
469	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
470	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
471	irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
472	ixp4xx_pci_preinit();
473}
474
475static void __init gmlr_pci_postinit(void)
476{
477	if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
478	    (hw_bits & CFG_HW_USB_PORTS) < 5) {
479		/* need to adjust number of USB ports on NEC chip */
480		u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
481		if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
482			value &= ~7;
483			value |= (hw_bits & CFG_HW_USB_PORTS);
484			ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
485		}
486	}
487}
488
489static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
490{
491	switch(slot) {
492	case SLOT_ETHA:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
493	case SLOT_ETHB:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
494	case SLOT_NEC:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
495	default:	return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
496	}
497}
498
499static struct hw_pci gmlr_hw_pci __initdata = {
500	.nr_controllers = 1,
501	.ops		= &ixp4xx_ops,
502	.preinit	= gmlr_pci_preinit,
503	.postinit	= gmlr_pci_postinit,
504	.setup		= ixp4xx_setup,
505	.map_irq	= gmlr_map_irq,
506};
507
508static int __init gmlr_pci_init(void)
509{
510	if (machine_is_goramo_mlr() &&
511	    (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
512		pci_common_init(&gmlr_hw_pci);
513	return 0;
514}
515
516subsys_initcall(gmlr_pci_init);
517#endif /* CONFIG_PCI */
518
519
520MACHINE_START(GORAMO_MLR, "MultiLink")
521	/* Maintainer: Krzysztof Halasa */
522	.map_io		= ixp4xx_map_io,
523	.init_early	= ixp4xx_init_early,
524	.init_irq	= ixp4xx_init_irq,
525	.init_time	= ixp4xx_timer_init,
526	.atag_offset	= 0x100,
527	.init_machine	= gmlr_init,
528#if defined(CONFIG_PCI)
529	.dma_zone_size	= SZ_64M,
530#endif
531	.restart	= ixp4xx_restart,
532MACHINE_END
533