18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * DSM-G600 board-level PCI initialization
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Copyright (C) 2006 Tower Technologies
68c2ecf20Sopenharmony_ci * Author: Alessandro Zummo <a.zummo@towertech.it>
78c2ecf20Sopenharmony_ci *
88c2ecf20Sopenharmony_ci * based on ixdp425-pci.c:
98c2ecf20Sopenharmony_ci *	Copyright (C) 2002 Intel Corporation.
108c2ecf20Sopenharmony_ci *	Copyright (C) 2003-2004 MontaVista Software, Inc.
118c2ecf20Sopenharmony_ci *
128c2ecf20Sopenharmony_ci * Maintainer: http://www.nslu2-linux.org/
138c2ecf20Sopenharmony_ci */
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci#include <linux/pci.h>
168c2ecf20Sopenharmony_ci#include <linux/init.h>
178c2ecf20Sopenharmony_ci#include <linux/irq.h>
188c2ecf20Sopenharmony_ci#include <asm/mach/pci.h>
198c2ecf20Sopenharmony_ci#include <asm/mach-types.h>
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci#include "irqs.h"
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci#define MAX_DEV		4
248c2ecf20Sopenharmony_ci#define IRQ_LINES	3
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci/* PCI controller GPIO to IRQ pin mappings */
278c2ecf20Sopenharmony_ci#define INTA		11
288c2ecf20Sopenharmony_ci#define INTB		10
298c2ecf20Sopenharmony_ci#define INTC		9
308c2ecf20Sopenharmony_ci#define INTD		8
318c2ecf20Sopenharmony_ci#define INTE		7
328c2ecf20Sopenharmony_ci#define INTF		6
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_civoid __init dsmg600_pci_preinit(void)
358c2ecf20Sopenharmony_ci{
368c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
378c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
388c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
398c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
408c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
418c2ecf20Sopenharmony_ci	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
428c2ecf20Sopenharmony_ci	ixp4xx_pci_preinit();
438c2ecf20Sopenharmony_ci}
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_cistatic int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
468c2ecf20Sopenharmony_ci{
478c2ecf20Sopenharmony_ci	static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
488c2ecf20Sopenharmony_ci		{ IXP4XX_GPIO_IRQ(INTE), -1, -1 },
498c2ecf20Sopenharmony_ci		{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
508c2ecf20Sopenharmony_ci		{ IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
518c2ecf20Sopenharmony_ci		  IXP4XX_GPIO_IRQ(INTD) },
528c2ecf20Sopenharmony_ci		{ IXP4XX_GPIO_IRQ(INTF), -1, -1 },
538c2ecf20Sopenharmony_ci	};
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ci	if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
568c2ecf20Sopenharmony_ci		return pci_irq_table[slot - 1][pin - 1];
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci	return -1;
598c2ecf20Sopenharmony_ci}
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_cistruct hw_pci __initdata dsmg600_pci = {
628c2ecf20Sopenharmony_ci	.nr_controllers = 1,
638c2ecf20Sopenharmony_ci	.ops		= &ixp4xx_ops,
648c2ecf20Sopenharmony_ci	.preinit	= dsmg600_pci_preinit,
658c2ecf20Sopenharmony_ci	.setup		= ixp4xx_setup,
668c2ecf20Sopenharmony_ci	.map_irq	= dsmg600_map_irq,
678c2ecf20Sopenharmony_ci};
688c2ecf20Sopenharmony_ci
698c2ecf20Sopenharmony_ciint __init dsmg600_pci_init(void)
708c2ecf20Sopenharmony_ci{
718c2ecf20Sopenharmony_ci	if (machine_is_dsmg600())
728c2ecf20Sopenharmony_ci		pci_common_init(&dsmg600_pci);
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_ci	return 0;
758c2ecf20Sopenharmony_ci}
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_cisubsys_initcall(dsmg600_pci_init);
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