18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * arch/arm/mach-footbridge/include/mach/memory.h 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 1996-1999 Russell King. 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Changelog: 88c2ecf20Sopenharmony_ci * 20-Oct-1996 RMK Created 98c2ecf20Sopenharmony_ci * 31-Dec-1997 RMK Fixed definitions to reduce warnings. 108c2ecf20Sopenharmony_ci * 17-May-1998 DAG Added __virt_to_bus and __bus_to_virt functions. 118c2ecf20Sopenharmony_ci * 21-Nov-1998 RMK Changed __virt_to_bus and __bus_to_virt to macros. 128c2ecf20Sopenharmony_ci * 21-Mar-1999 RMK Added PAGE_OFFSET for co285 architecture. 138c2ecf20Sopenharmony_ci * Renamed to memory.h 148c2ecf20Sopenharmony_ci * Moved PAGE_OFFSET and TASK_SIZE here 158c2ecf20Sopenharmony_ci */ 168c2ecf20Sopenharmony_ci#ifndef __ASM_ARCH_MEMORY_H 178c2ecf20Sopenharmony_ci#define __ASM_ARCH_MEMORY_H 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci#if defined(CONFIG_FOOTBRIDGE_ADDIN) 218c2ecf20Sopenharmony_ci/* 228c2ecf20Sopenharmony_ci * If we may be using add-in footbridge mode, then we must 238c2ecf20Sopenharmony_ci * use the out-of-line translation that makes use of the 248c2ecf20Sopenharmony_ci * PCI BAR 258c2ecf20Sopenharmony_ci */ 268c2ecf20Sopenharmony_ci#ifndef __ASSEMBLY__ 278c2ecf20Sopenharmony_ciextern unsigned long __virt_to_bus(unsigned long); 288c2ecf20Sopenharmony_ciextern unsigned long __bus_to_virt(unsigned long); 298c2ecf20Sopenharmony_ciextern unsigned long __pfn_to_bus(unsigned long); 308c2ecf20Sopenharmony_ciextern unsigned long __bus_to_pfn(unsigned long); 318c2ecf20Sopenharmony_ci#endif 328c2ecf20Sopenharmony_ci#define __virt_to_bus __virt_to_bus 338c2ecf20Sopenharmony_ci#define __bus_to_virt __bus_to_virt 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci#elif defined(CONFIG_FOOTBRIDGE_HOST) 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci/* 388c2ecf20Sopenharmony_ci * The footbridge is programmed to expose the system RAM at 0xe0000000. 398c2ecf20Sopenharmony_ci * The requirement is that the RAM isn't placed at bus address 0, which 408c2ecf20Sopenharmony_ci * would clash with VGA cards. 418c2ecf20Sopenharmony_ci */ 428c2ecf20Sopenharmony_ci#define BUS_OFFSET 0xe0000000 438c2ecf20Sopenharmony_ci#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) 448c2ecf20Sopenharmony_ci#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) 458c2ecf20Sopenharmony_ci#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET)) 468c2ecf20Sopenharmony_ci#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET)) 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci#else 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci#error "Undefined footbridge mode" 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#endif 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci/* 558c2ecf20Sopenharmony_ci * Cache flushing area. 568c2ecf20Sopenharmony_ci */ 578c2ecf20Sopenharmony_ci#define FLUSH_BASE 0xf9000000 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci#define FLUSH_BASE_PHYS 0x50000000 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#endif 62