1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * arch/arm/mach-ep93xx/soc.h
4 *
5 * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
6 * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
7 */
8
9#ifndef _EP93XX_SOC_H
10#define _EP93XX_SOC_H
11
12#include <mach/ep93xx-regs.h>
13
14/*
15 * EP93xx Physical Memory Map:
16 *
17 * The ASDO pin is sampled at system reset to select a synchronous or
18 * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
19 * the synchronous boot mode is selected.  When ASDO is "0" (i.e
20 * pulled-down) the asynchronous boot mode is selected.
21 *
22 * In synchronous boot mode nSDCE3 is decoded starting at physical address
23 * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
24 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
25 * decoded at 0xf0000000.
26 *
27 * There is known errata for the EP93xx dealing with External Memory
28 * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
29 * Guidelines" for more information.  This document can be found at:
30 *
31 *	http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
32 */
33
34#define EP93XX_CS0_PHYS_BASE_ASYNC	0x00000000	/* ASDO Pin = 0 */
35#define EP93XX_SDCE3_PHYS_BASE_SYNC	0x00000000	/* ASDO Pin = 1 */
36#define EP93XX_CS1_PHYS_BASE		0x10000000
37#define EP93XX_CS2_PHYS_BASE		0x20000000
38#define EP93XX_CS3_PHYS_BASE		0x30000000
39#define EP93XX_PCMCIA_PHYS_BASE		0x40000000
40#define EP93XX_CS6_PHYS_BASE		0x60000000
41#define EP93XX_CS7_PHYS_BASE		0x70000000
42#define EP93XX_SDCE0_PHYS_BASE		0xc0000000
43#define EP93XX_SDCE1_PHYS_BASE		0xd0000000
44#define EP93XX_SDCE2_PHYS_BASE		0xe0000000
45#define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
46#define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */
47
48/* AHB peripherals */
49#define EP93XX_DMA_BASE			EP93XX_AHB_IOMEM(0x00000000)
50
51#define EP93XX_ETHERNET_PHYS_BASE	EP93XX_AHB_PHYS(0x00010000)
52#define EP93XX_ETHERNET_BASE		EP93XX_AHB_IOMEM(0x00010000)
53
54#define EP93XX_USB_PHYS_BASE		EP93XX_AHB_PHYS(0x00020000)
55#define EP93XX_USB_BASE			EP93XX_AHB_IOMEM(0x00020000)
56
57#define EP93XX_RASTER_PHYS_BASE		EP93XX_AHB_PHYS(0x00030000)
58#define EP93XX_RASTER_BASE		EP93XX_AHB_IOMEM(0x00030000)
59
60#define EP93XX_GRAPHICS_ACCEL_BASE	EP93XX_AHB_IOMEM(0x00040000)
61
62#define EP93XX_SDRAM_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00060000)
63
64#define EP93XX_PCMCIA_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00080000)
65
66#define EP93XX_BOOT_ROM_BASE		EP93XX_AHB_IOMEM(0x00090000)
67
68#define EP93XX_IDE_PHYS_BASE		EP93XX_AHB_PHYS(0x000a0000)
69#define EP93XX_IDE_BASE			EP93XX_AHB_IOMEM(0x000a0000)
70
71#define EP93XX_VIC1_BASE		EP93XX_AHB_IOMEM(0x000b0000)
72
73#define EP93XX_VIC2_BASE		EP93XX_AHB_IOMEM(0x000c0000)
74
75/* APB peripherals */
76#define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
77
78#define EP93XX_I2S_PHYS_BASE		EP93XX_APB_PHYS(0x00020000)
79#define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)
80
81#define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
82
83#define EP93XX_AAC_PHYS_BASE		EP93XX_APB_PHYS(0x00080000)
84#define EP93XX_AAC_BASE			EP93XX_APB_IOMEM(0x00080000)
85
86#define EP93XX_SPI_PHYS_BASE		EP93XX_APB_PHYS(0x000a0000)
87#define EP93XX_SPI_BASE			EP93XX_APB_IOMEM(0x000a0000)
88
89#define EP93XX_IRDA_BASE		EP93XX_APB_IOMEM(0x000b0000)
90
91#define EP93XX_KEY_MATRIX_PHYS_BASE	EP93XX_APB_PHYS(0x000f0000)
92#define EP93XX_KEY_MATRIX_BASE		EP93XX_APB_IOMEM(0x000f0000)
93
94#define EP93XX_ADC_PHYS_BASE		EP93XX_APB_PHYS(0x00100000)
95#define EP93XX_ADC_BASE			EP93XX_APB_IOMEM(0x00100000)
96#define EP93XX_TOUCHSCREEN_BASE		EP93XX_APB_IOMEM(0x00100000)
97
98#define EP93XX_PWM_PHYS_BASE		EP93XX_APB_PHYS(0x00110000)
99#define EP93XX_PWM_BASE			EP93XX_APB_IOMEM(0x00110000)
100
101#define EP93XX_RTC_PHYS_BASE		EP93XX_APB_PHYS(0x00120000)
102#define EP93XX_RTC_BASE			EP93XX_APB_IOMEM(0x00120000)
103
104#define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
105#define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
106
107/* System controller */
108#define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)
109#define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
110#define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
111#define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)
112#define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)
113#define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)
114#define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)
115#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)
116#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)
117#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)
118#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)
119#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)
120#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)
121#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)
122#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)
123#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)
124#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)
125#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)
126#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
127#define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
128#define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
129#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
130#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
131#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
132#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
133#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
134#define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
135#define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
136#define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)
137#define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)
138#define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)
139#define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)
140#define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)
141#define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)
142#define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)
143#define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)
144#define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)
145#define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)
146#define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)
147#define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)
148#define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)
149#define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)
150#define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)
151#define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)
152#define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)
153#define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)
154#define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)
155#define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)
156#define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)
157#define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)
158#define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)
159#define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)
160#define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)
161#define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)
162#define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)
163#define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)
164#define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)
165#define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)
166#define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)
167#define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
168#define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
169#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
170#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
171#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
172#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
173#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
174#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
175#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
176#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
177#define EP93XX_I2SCLKDIV_LRDIV128	(2 << 17)
178#define EP93XX_I2SCLKDIV_LRDIV_MASK	(3 << 17)
179#define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
180#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
181#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
182#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)
183#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)
184#define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)
185#define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)
186#define EP93XX_SYSCON_SYSCFG_REV_SHIFT	(28)
187#define EP93XX_SYSCON_SYSCFG_SBOOT	(1<<8)
188#define EP93XX_SYSCON_SYSCFG_LCSN7	(1<<7)
189#define EP93XX_SYSCON_SYSCFG_LCSN6	(1<<6)
190#define EP93XX_SYSCON_SYSCFG_LASDO	(1<<5)
191#define EP93XX_SYSCON_SYSCFG_LEEDA	(1<<4)
192#define EP93XX_SYSCON_SYSCFG_LEECLK	(1<<3)
193#define EP93XX_SYSCON_SYSCFG_LCSN2	(1<<1)
194#define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)
195#define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
196
197/* EP93xx System Controller software locked register write */
198void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
199void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
200
201static inline void ep93xx_devcfg_set_bits(unsigned int bits)
202{
203	ep93xx_devcfg_set_clear(bits, 0x00);
204}
205
206static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
207{
208	ep93xx_devcfg_set_clear(0x00, bits);
209}
210
211#endif /* _EP93XX_SOC_H */
212