18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * arch/arm/mach-ep93xx/include/mach/hardware.h 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef __ASM_ARCH_HARDWARE_H 78c2ecf20Sopenharmony_ci#define __ASM_ARCH_HARDWARE_H 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include "platform.h" 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* 128c2ecf20Sopenharmony_ci * The EP93xx has two external crystal oscillators. To generate the 138c2ecf20Sopenharmony_ci * required high-frequency clocks, the processor uses two phase-locked- 148c2ecf20Sopenharmony_ci * loops (PLLs) to multiply the incoming external clock signal to much 158c2ecf20Sopenharmony_ci * higher frequencies that are then divided down by programmable dividers 168c2ecf20Sopenharmony_ci * to produce the needed clocks. The PLLs operate independently of one 178c2ecf20Sopenharmony_ci * another. 188c2ecf20Sopenharmony_ci */ 198c2ecf20Sopenharmony_ci#define EP93XX_EXT_CLK_RATE 14745600 208c2ecf20Sopenharmony_ci#define EP93XX_EXT_RTC_RATE 32768 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) 238c2ecf20Sopenharmony_ci#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#endif 26