1/*
2 * arch/arm/mach-dove/pcie.c
3 *
4 * PCIe functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/clk.h>
14#include <video/vga.h>
15#include <asm/mach/pci.h>
16#include <asm/mach/arch.h>
17#include <asm/setup.h>
18#include <asm/delay.h>
19#include <plat/pcie.h>
20#include <plat/addr-map.h>
21#include "irqs.h"
22#include "bridge-regs.h"
23#include "common.h"
24
25struct pcie_port {
26	u8			index;
27	u8			root_bus_nr;
28	void __iomem		*base;
29	spinlock_t		conf_lock;
30	char			mem_space_name[16];
31	struct resource		res;
32};
33
34static struct pcie_port pcie_port[2];
35static int num_pcie_ports;
36
37
38static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
39{
40	struct pcie_port *pp;
41
42	if (nr >= num_pcie_ports)
43		return 0;
44
45	pp = &pcie_port[nr];
46	sys->private_data = pp;
47	pp->root_bus_nr = sys->busnr;
48
49	/*
50	 * Generic PCIe unit setup.
51	 */
52	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
53
54	orion_pcie_setup(pp->base);
55
56	if (pp->index == 0)
57		pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
58	else
59		pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
60
61	/*
62	 * IORESOURCE_MEM
63	 */
64	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
65		 "PCIe %d MEM", pp->index);
66	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
67	pp->res.name = pp->mem_space_name;
68	if (pp->index == 0) {
69		pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
70		pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
71	} else {
72		pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
73		pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
74	}
75	pp->res.flags = IORESOURCE_MEM;
76	if (request_resource(&iomem_resource, &pp->res))
77		panic("Request PCIe Memory resource failed\n");
78	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
79
80	return 1;
81}
82
83static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
84{
85	/*
86	 * Don't go out when trying to access nonexisting devices
87	 * on the local bus.
88	 */
89	if (bus == pp->root_bus_nr && dev > 1)
90		return 0;
91
92	return 1;
93}
94
95static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
96			int size, u32 *val)
97{
98	struct pci_sys_data *sys = bus->sysdata;
99	struct pcie_port *pp = sys->private_data;
100	unsigned long flags;
101	int ret;
102
103	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
104		*val = 0xffffffff;
105		return PCIBIOS_DEVICE_NOT_FOUND;
106	}
107
108	spin_lock_irqsave(&pp->conf_lock, flags);
109	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
110	spin_unlock_irqrestore(&pp->conf_lock, flags);
111
112	return ret;
113}
114
115static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
116			int where, int size, u32 val)
117{
118	struct pci_sys_data *sys = bus->sysdata;
119	struct pcie_port *pp = sys->private_data;
120	unsigned long flags;
121	int ret;
122
123	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
124		return PCIBIOS_DEVICE_NOT_FOUND;
125
126	spin_lock_irqsave(&pp->conf_lock, flags);
127	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
128	spin_unlock_irqrestore(&pp->conf_lock, flags);
129
130	return ret;
131}
132
133static struct pci_ops pcie_ops = {
134	.read = pcie_rd_conf,
135	.write = pcie_wr_conf,
136};
137
138static void rc_pci_fixup(struct pci_dev *dev)
139{
140	/*
141	 * Prevent enumeration of root complex.
142	 */
143	if (dev->bus->parent == NULL && dev->devfn == 0) {
144		int i;
145
146		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
147			dev->resource[i].start = 0;
148			dev->resource[i].end   = 0;
149			dev->resource[i].flags = 0;
150		}
151	}
152}
153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
154
155static int __init
156dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
157{
158	struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
159
160	if (nr >= num_pcie_ports) {
161		BUG();
162		return -EINVAL;
163	}
164
165	list_splice_init(&sys->resources, &bridge->windows);
166	bridge->dev.parent = NULL;
167	bridge->sysdata = sys;
168	bridge->busnr = sys->busnr;
169	bridge->ops = &pcie_ops;
170
171	return pci_scan_root_bus_bridge(bridge);
172}
173
174static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
175{
176	struct pci_sys_data *sys = dev->sysdata;
177	struct pcie_port *pp = sys->private_data;
178
179	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
180}
181
182static struct hw_pci dove_pci __initdata = {
183	.nr_controllers	= 2,
184	.setup		= dove_pcie_setup,
185	.scan		= dove_pcie_scan_bus,
186	.map_irq	= dove_pcie_map_irq,
187};
188
189static void __init add_pcie_port(int index, void __iomem *base)
190{
191	printk(KERN_INFO "Dove PCIe port %d: ", index);
192
193	if (orion_pcie_link_up(base)) {
194		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
195		struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
196
197		if (!IS_ERR(clk))
198			clk_prepare_enable(clk);
199
200		printk(KERN_INFO "link up\n");
201
202		pp->index = index;
203		pp->root_bus_nr = -1;
204		pp->base = base;
205		spin_lock_init(&pp->conf_lock);
206		memset(&pp->res, 0, sizeof(pp->res));
207	} else {
208		printk(KERN_INFO "link down, ignoring\n");
209	}
210}
211
212void __init dove_pcie_init(int init_port0, int init_port1)
213{
214	vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
215
216	if (init_port0)
217		add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
218
219	if (init_port1)
220		add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
221
222	pci_common_init(&dove_pci);
223}
224