1/*
2 * Mbus-L to Mbus Bridge Registers
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2.  This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_BRIDGE_REGS_H
10#define __ASM_ARCH_BRIDGE_REGS_H
11
12#include "dove.h"
13
14#define CPU_CONFIG		(BRIDGE_VIRT_BASE + 0x0000)
15
16#define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
17#define  CPU_CTRL_PCIE0_LINK	0x00000001
18#define  CPU_RESET		0x00000002
19#define  CPU_CTRL_PCIE1_LINK	0x00000008
20
21#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
22#define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)
23#define  SOFT_RESET_OUT_EN	0x00000004
24
25#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
26#define  SOFT_RESET		0x00000001
27
28#define BRIDGE_CAUSE		(BRIDGE_VIRT_BASE + 0x0110)
29#define  BRIDGE_INT_TIMER1_CLR	(~0x0004)
30
31#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
32#define IRQ_CAUSE_LOW_OFF	0x0000
33#define IRQ_MASK_LOW_OFF	0x0004
34#define FIQ_MASK_LOW_OFF	0x0008
35#define ENDPOINT_MASK_LOW_OFF	0x000c
36#define IRQ_CAUSE_HIGH_OFF	0x0010
37#define IRQ_MASK_HIGH_OFF	0x0014
38#define FIQ_MASK_HIGH_OFF	0x0018
39#define ENDPOINT_MASK_HIGH_OFF	0x001c
40#define PCIE_INTERRUPT_MASK_OFF	0x0020
41
42#define IRQ_MASK_LOW		(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
43#define FIQ_MASK_LOW		(IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
44#define ENDPOINT_MASK_LOW	(IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
45#define IRQ_MASK_HIGH		(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
46#define FIQ_MASK_HIGH		(IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
47#define ENDPOINT_MASK_HIGH	(IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
48#define PCIE_INTERRUPT_MASK	(IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
49
50#define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE + 0x011c)
51
52#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
53#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
54
55#endif
56