18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * Mbus-L to Mbus Bridge Registers 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public 58c2ecf20Sopenharmony_ci * License version 2. This program is licensed "as is" without any 68c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied. 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#ifndef __ASM_ARCH_BRIDGE_REGS_H 108c2ecf20Sopenharmony_ci#define __ASM_ARCH_BRIDGE_REGS_H 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include "dove.h" 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) 178c2ecf20Sopenharmony_ci#define CPU_CTRL_PCIE0_LINK 0x00000001 188c2ecf20Sopenharmony_ci#define CPU_RESET 0x00000002 198c2ecf20Sopenharmony_ci#define CPU_CTRL_PCIE1_LINK 0x00000008 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) 228c2ecf20Sopenharmony_ci#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) 238c2ecf20Sopenharmony_ci#define SOFT_RESET_OUT_EN 0x00000004 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) 268c2ecf20Sopenharmony_ci#define SOFT_RESET 0x00000001 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) 298c2ecf20Sopenharmony_ci#define BRIDGE_INT_TIMER1_CLR (~0x0004) 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) 328c2ecf20Sopenharmony_ci#define IRQ_CAUSE_LOW_OFF 0x0000 338c2ecf20Sopenharmony_ci#define IRQ_MASK_LOW_OFF 0x0004 348c2ecf20Sopenharmony_ci#define FIQ_MASK_LOW_OFF 0x0008 358c2ecf20Sopenharmony_ci#define ENDPOINT_MASK_LOW_OFF 0x000c 368c2ecf20Sopenharmony_ci#define IRQ_CAUSE_HIGH_OFF 0x0010 378c2ecf20Sopenharmony_ci#define IRQ_MASK_HIGH_OFF 0x0014 388c2ecf20Sopenharmony_ci#define FIQ_MASK_HIGH_OFF 0x0018 398c2ecf20Sopenharmony_ci#define ENDPOINT_MASK_HIGH_OFF 0x001c 408c2ecf20Sopenharmony_ci#define PCIE_INTERRUPT_MASK_OFF 0x0020 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) 438c2ecf20Sopenharmony_ci#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) 448c2ecf20Sopenharmony_ci#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) 458c2ecf20Sopenharmony_ci#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) 468c2ecf20Sopenharmony_ci#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) 478c2ecf20Sopenharmony_ci#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) 488c2ecf20Sopenharmony_ci#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) 538c2ecf20Sopenharmony_ci#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci#endif 56