1/* 2 * TI DaVinci DM646x chip specific setup 3 * 4 * Author: Kevin Hilman, Deep Root Systems, LLC 5 * 6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 */ 11 12#include <linux/clk-provider.h> 13#include <linux/clk/davinci.h> 14#include <linux/clkdev.h> 15#include <linux/dma-mapping.h> 16#include <linux/dmaengine.h> 17#include <linux/init.h> 18#include <linux/io.h> 19#include <linux/irqchip/irq-davinci-aintc.h> 20#include <linux/platform_data/edma.h> 21#include <linux/platform_data/gpio-davinci.h> 22#include <linux/platform_device.h> 23#include <linux/serial_8250.h> 24 25#include <asm/mach/map.h> 26 27#include <mach/common.h> 28#include <mach/cputype.h> 29#include <mach/mux.h> 30#include <mach/serial.h> 31 32#include <clocksource/timer-davinci.h> 33 34#include "asp.h" 35#include "davinci.h" 36#include "irqs.h" 37#include "mux.h" 38 39#define DAVINCI_VPIF_BASE (0x01C12000) 40 41#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ 42 BIT_MASK(0)) 43#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ 44 BIT_MASK(8)) 45 46#define DM646X_EMAC_BASE 0x01c80000 47#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) 48#define DM646X_EMAC_CNTRL_OFFSET 0x0000 49#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000 50#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000 51#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000 52 53static struct emac_platform_data dm646x_emac_pdata = { 54 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, 55 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, 56 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, 57 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, 58 .version = EMAC_VERSION_2, 59}; 60 61static struct resource dm646x_emac_resources[] = { 62 { 63 .start = DM646X_EMAC_BASE, 64 .end = DM646X_EMAC_BASE + SZ_16K - 1, 65 .flags = IORESOURCE_MEM, 66 }, 67 { 68 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT), 69 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT), 70 .flags = IORESOURCE_IRQ, 71 }, 72 { 73 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT), 74 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT), 75 .flags = IORESOURCE_IRQ, 76 }, 77 { 78 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT), 79 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT), 80 .flags = IORESOURCE_IRQ, 81 }, 82 { 83 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT), 84 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT), 85 .flags = IORESOURCE_IRQ, 86 }, 87}; 88 89static struct platform_device dm646x_emac_device = { 90 .name = "davinci_emac", 91 .id = 1, 92 .dev = { 93 .platform_data = &dm646x_emac_pdata, 94 }, 95 .num_resources = ARRAY_SIZE(dm646x_emac_resources), 96 .resource = dm646x_emac_resources, 97}; 98 99static struct resource dm646x_mdio_resources[] = { 100 { 101 .start = DM646X_EMAC_MDIO_BASE, 102 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1, 103 .flags = IORESOURCE_MEM, 104 }, 105}; 106 107static struct platform_device dm646x_mdio_device = { 108 .name = "davinci_mdio", 109 .id = 0, 110 .num_resources = ARRAY_SIZE(dm646x_mdio_resources), 111 .resource = dm646x_mdio_resources, 112}; 113 114/* 115 * Device specific mux setup 116 * 117 * soc description mux mode mode mux dbg 118 * reg offset mask mode 119 */ 120static const struct mux_config dm646x_pins[] = { 121#ifdef CONFIG_DAVINCI_MUX 122MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) 123 124MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) 125 126MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) 127 128MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) 129 130MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) 131 132MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) 133 134MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) 135 136MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) 137 138MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) 139 140MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) 141 142MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) 143 144MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) 145 146MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) 147 148MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) 149#endif 150}; 151 152static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { 153 [IRQ_DM646X_VP_VERTINT0] = 7, 154 [IRQ_DM646X_VP_VERTINT1] = 7, 155 [IRQ_DM646X_VP_VERTINT2] = 7, 156 [IRQ_DM646X_VP_VERTINT3] = 7, 157 [IRQ_DM646X_VP_ERRINT] = 7, 158 [IRQ_DM646X_RESERVED_1] = 7, 159 [IRQ_DM646X_RESERVED_2] = 7, 160 [IRQ_DM646X_WDINT] = 7, 161 [IRQ_DM646X_CRGENINT0] = 7, 162 [IRQ_DM646X_CRGENINT1] = 7, 163 [IRQ_DM646X_TSIFINT0] = 7, 164 [IRQ_DM646X_TSIFINT1] = 7, 165 [IRQ_DM646X_VDCEINT] = 7, 166 [IRQ_DM646X_USBINT] = 7, 167 [IRQ_DM646X_USBDMAINT] = 7, 168 [IRQ_DM646X_PCIINT] = 7, 169 [IRQ_CCINT0] = 7, /* dma */ 170 [IRQ_CCERRINT] = 7, /* dma */ 171 [IRQ_TCERRINT0] = 7, /* dma */ 172 [IRQ_TCERRINT] = 7, /* dma */ 173 [IRQ_DM646X_TCERRINT2] = 7, 174 [IRQ_DM646X_TCERRINT3] = 7, 175 [IRQ_DM646X_IDE] = 7, 176 [IRQ_DM646X_HPIINT] = 7, 177 [IRQ_DM646X_EMACRXTHINT] = 7, 178 [IRQ_DM646X_EMACRXINT] = 7, 179 [IRQ_DM646X_EMACTXINT] = 7, 180 [IRQ_DM646X_EMACMISCINT] = 7, 181 [IRQ_DM646X_MCASP0TXINT] = 7, 182 [IRQ_DM646X_MCASP0RXINT] = 7, 183 [IRQ_DM646X_RESERVED_3] = 7, 184 [IRQ_DM646X_MCASP1TXINT] = 7, 185 [IRQ_TINT0_TINT12] = 7, /* clockevent */ 186 [IRQ_TINT0_TINT34] = 7, /* clocksource */ 187 [IRQ_TINT1_TINT12] = 7, /* DSP timer */ 188 [IRQ_TINT1_TINT34] = 7, /* system tick */ 189 [IRQ_PWMINT0] = 7, 190 [IRQ_PWMINT1] = 7, 191 [IRQ_DM646X_VLQINT] = 7, 192 [IRQ_I2C] = 7, 193 [IRQ_UARTINT0] = 7, 194 [IRQ_UARTINT1] = 7, 195 [IRQ_DM646X_UARTINT2] = 7, 196 [IRQ_DM646X_SPINT0] = 7, 197 [IRQ_DM646X_SPINT1] = 7, 198 [IRQ_DM646X_DSP2ARMINT] = 7, 199 [IRQ_DM646X_RESERVED_4] = 7, 200 [IRQ_DM646X_PSCINT] = 7, 201 [IRQ_DM646X_GPIO0] = 7, 202 [IRQ_DM646X_GPIO1] = 7, 203 [IRQ_DM646X_GPIO2] = 7, 204 [IRQ_DM646X_GPIO3] = 7, 205 [IRQ_DM646X_GPIO4] = 7, 206 [IRQ_DM646X_GPIO5] = 7, 207 [IRQ_DM646X_GPIO6] = 7, 208 [IRQ_DM646X_GPIO7] = 7, 209 [IRQ_DM646X_GPIOBNK0] = 7, 210 [IRQ_DM646X_GPIOBNK1] = 7, 211 [IRQ_DM646X_GPIOBNK2] = 7, 212 [IRQ_DM646X_DDRINT] = 7, 213 [IRQ_DM646X_AEMIFINT] = 7, 214 [IRQ_COMMTX] = 7, 215 [IRQ_COMMRX] = 7, 216 [IRQ_EMUINT] = 7, 217}; 218 219/*----------------------------------------------------------------------*/ 220 221/* Four Transfer Controllers on DM646x */ 222static s8 dm646x_queue_priority_mapping[][2] = { 223 /* {event queue no, Priority} */ 224 {0, 4}, 225 {1, 0}, 226 {2, 5}, 227 {3, 1}, 228 {-1, -1}, 229}; 230 231static const struct dma_slave_map dm646x_edma_map[] = { 232 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) }, 233 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) }, 234 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) }, 235 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) }, 236 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) }, 237}; 238 239static struct edma_soc_info dm646x_edma_pdata = { 240 .queue_priority_mapping = dm646x_queue_priority_mapping, 241 .default_queue = EVENTQ_1, 242 .slave_map = dm646x_edma_map, 243 .slavecnt = ARRAY_SIZE(dm646x_edma_map), 244}; 245 246static struct resource edma_resources[] = { 247 { 248 .name = "edma3_cc", 249 .start = 0x01c00000, 250 .end = 0x01c00000 + SZ_64K - 1, 251 .flags = IORESOURCE_MEM, 252 }, 253 { 254 .name = "edma3_tc0", 255 .start = 0x01c10000, 256 .end = 0x01c10000 + SZ_1K - 1, 257 .flags = IORESOURCE_MEM, 258 }, 259 { 260 .name = "edma3_tc1", 261 .start = 0x01c10400, 262 .end = 0x01c10400 + SZ_1K - 1, 263 .flags = IORESOURCE_MEM, 264 }, 265 { 266 .name = "edma3_tc2", 267 .start = 0x01c10800, 268 .end = 0x01c10800 + SZ_1K - 1, 269 .flags = IORESOURCE_MEM, 270 }, 271 { 272 .name = "edma3_tc3", 273 .start = 0x01c10c00, 274 .end = 0x01c10c00 + SZ_1K - 1, 275 .flags = IORESOURCE_MEM, 276 }, 277 { 278 .name = "edma3_ccint", 279 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), 280 .flags = IORESOURCE_IRQ, 281 }, 282 { 283 .name = "edma3_ccerrint", 284 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), 285 .flags = IORESOURCE_IRQ, 286 }, 287 /* not using TC*_ERR */ 288}; 289 290static const struct platform_device_info dm646x_edma_device __initconst = { 291 .name = "edma", 292 .id = 0, 293 .dma_mask = DMA_BIT_MASK(32), 294 .res = edma_resources, 295 .num_res = ARRAY_SIZE(edma_resources), 296 .data = &dm646x_edma_pdata, 297 .size_data = sizeof(dm646x_edma_pdata), 298}; 299 300static struct resource dm646x_mcasp0_resources[] = { 301 { 302 .name = "mpu", 303 .start = DAVINCI_DM646X_MCASP0_REG_BASE, 304 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, 305 .flags = IORESOURCE_MEM, 306 }, 307 { 308 .name = "tx", 309 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, 310 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, 311 .flags = IORESOURCE_DMA, 312 }, 313 { 314 .name = "rx", 315 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, 316 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, 317 .flags = IORESOURCE_DMA, 318 }, 319 { 320 .name = "tx", 321 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT), 322 .flags = IORESOURCE_IRQ, 323 }, 324 { 325 .name = "rx", 326 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT), 327 .flags = IORESOURCE_IRQ, 328 }, 329}; 330 331/* DIT mode only, rx is not supported */ 332static struct resource dm646x_mcasp1_resources[] = { 333 { 334 .name = "mpu", 335 .start = DAVINCI_DM646X_MCASP1_REG_BASE, 336 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, 337 .flags = IORESOURCE_MEM, 338 }, 339 { 340 .name = "tx", 341 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, 342 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, 343 .flags = IORESOURCE_DMA, 344 }, 345 { 346 .name = "tx", 347 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT), 348 .flags = IORESOURCE_IRQ, 349 }, 350}; 351 352static struct platform_device dm646x_mcasp0_device = { 353 .name = "davinci-mcasp", 354 .id = 0, 355 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), 356 .resource = dm646x_mcasp0_resources, 357}; 358 359static struct platform_device dm646x_mcasp1_device = { 360 .name = "davinci-mcasp", 361 .id = 1, 362 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), 363 .resource = dm646x_mcasp1_resources, 364}; 365 366static struct platform_device dm646x_dit_device = { 367 .name = "spdif-dit", 368 .id = -1, 369}; 370 371static u64 vpif_dma_mask = DMA_BIT_MASK(32); 372 373static struct resource vpif_resource[] = { 374 { 375 .start = DAVINCI_VPIF_BASE, 376 .end = DAVINCI_VPIF_BASE + 0x03ff, 377 .flags = IORESOURCE_MEM, 378 } 379}; 380 381static struct platform_device vpif_dev = { 382 .name = "vpif", 383 .id = -1, 384 .dev = { 385 .dma_mask = &vpif_dma_mask, 386 .coherent_dma_mask = DMA_BIT_MASK(32), 387 }, 388 .resource = vpif_resource, 389 .num_resources = ARRAY_SIZE(vpif_resource), 390}; 391 392static struct resource vpif_display_resource[] = { 393 { 394 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2), 395 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2), 396 .flags = IORESOURCE_IRQ, 397 }, 398 { 399 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3), 400 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3), 401 .flags = IORESOURCE_IRQ, 402 }, 403}; 404 405static struct platform_device vpif_display_dev = { 406 .name = "vpif_display", 407 .id = -1, 408 .dev = { 409 .dma_mask = &vpif_dma_mask, 410 .coherent_dma_mask = DMA_BIT_MASK(32), 411 }, 412 .resource = vpif_display_resource, 413 .num_resources = ARRAY_SIZE(vpif_display_resource), 414}; 415 416static struct resource vpif_capture_resource[] = { 417 { 418 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0), 419 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0), 420 .flags = IORESOURCE_IRQ, 421 }, 422 { 423 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1), 424 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1), 425 .flags = IORESOURCE_IRQ, 426 }, 427}; 428 429static struct platform_device vpif_capture_dev = { 430 .name = "vpif_capture", 431 .id = -1, 432 .dev = { 433 .dma_mask = &vpif_dma_mask, 434 .coherent_dma_mask = DMA_BIT_MASK(32), 435 }, 436 .resource = vpif_capture_resource, 437 .num_resources = ARRAY_SIZE(vpif_capture_resource), 438}; 439 440static struct resource dm646x_gpio_resources[] = { 441 { /* registers */ 442 .start = DAVINCI_GPIO_BASE, 443 .end = DAVINCI_GPIO_BASE + SZ_4K - 1, 444 .flags = IORESOURCE_MEM, 445 }, 446 { /* interrupt */ 447 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0), 448 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0), 449 .flags = IORESOURCE_IRQ, 450 }, 451 { 452 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1), 453 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1), 454 .flags = IORESOURCE_IRQ, 455 }, 456 { 457 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2), 458 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2), 459 .flags = IORESOURCE_IRQ, 460 }, 461}; 462 463static struct davinci_gpio_platform_data dm646x_gpio_platform_data = { 464 .no_auto_base = true, 465 .base = 0, 466 .ngpio = 43, 467}; 468 469int __init dm646x_gpio_register(void) 470{ 471 return davinci_gpio_register(dm646x_gpio_resources, 472 ARRAY_SIZE(dm646x_gpio_resources), 473 &dm646x_gpio_platform_data); 474} 475/*----------------------------------------------------------------------*/ 476 477static struct map_desc dm646x_io_desc[] = { 478 { 479 .virtual = IO_VIRT, 480 .pfn = __phys_to_pfn(IO_PHYS), 481 .length = IO_SIZE, 482 .type = MT_DEVICE 483 }, 484}; 485 486/* Contents of JTAG ID register used to identify exact cpu type */ 487static struct davinci_id dm646x_ids[] = { 488 { 489 .variant = 0x0, 490 .part_no = 0xb770, 491 .manufacturer = 0x017, 492 .cpu_id = DAVINCI_CPU_ID_DM6467, 493 .name = "dm6467_rev1.x", 494 }, 495 { 496 .variant = 0x1, 497 .part_no = 0xb770, 498 .manufacturer = 0x017, 499 .cpu_id = DAVINCI_CPU_ID_DM6467, 500 .name = "dm6467_rev3.x", 501 }, 502}; 503 504/* 505 * Bottom half of timer0 is used for clockevent, top half is used for 506 * clocksource. 507 */ 508static const struct davinci_timer_cfg dm646x_timer_cfg = { 509 .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), 510 .irq = { 511 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), 512 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), 513 }, 514}; 515 516static struct plat_serial8250_port dm646x_serial0_platform_data[] = { 517 { 518 .mapbase = DAVINCI_UART0_BASE, 519 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), 520 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 521 UPF_IOREMAP, 522 .iotype = UPIO_MEM32, 523 .regshift = 2, 524 }, 525 { 526 .flags = 0, 527 } 528}; 529static struct plat_serial8250_port dm646x_serial1_platform_data[] = { 530 { 531 .mapbase = DAVINCI_UART1_BASE, 532 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), 533 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 534 UPF_IOREMAP, 535 .iotype = UPIO_MEM32, 536 .regshift = 2, 537 }, 538 { 539 .flags = 0, 540 } 541}; 542static struct plat_serial8250_port dm646x_serial2_platform_data[] = { 543 { 544 .mapbase = DAVINCI_UART2_BASE, 545 .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2), 546 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 547 UPF_IOREMAP, 548 .iotype = UPIO_MEM32, 549 .regshift = 2, 550 }, 551 { 552 .flags = 0, 553 } 554}; 555 556struct platform_device dm646x_serial_device[] = { 557 { 558 .name = "serial8250", 559 .id = PLAT8250_DEV_PLATFORM, 560 .dev = { 561 .platform_data = dm646x_serial0_platform_data, 562 } 563 }, 564 { 565 .name = "serial8250", 566 .id = PLAT8250_DEV_PLATFORM1, 567 .dev = { 568 .platform_data = dm646x_serial1_platform_data, 569 } 570 }, 571 { 572 .name = "serial8250", 573 .id = PLAT8250_DEV_PLATFORM2, 574 .dev = { 575 .platform_data = dm646x_serial2_platform_data, 576 } 577 }, 578 { 579 } 580}; 581 582static const struct davinci_soc_info davinci_soc_info_dm646x = { 583 .io_desc = dm646x_io_desc, 584 .io_desc_num = ARRAY_SIZE(dm646x_io_desc), 585 .jtag_id_reg = 0x01c40028, 586 .ids = dm646x_ids, 587 .ids_num = ARRAY_SIZE(dm646x_ids), 588 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 589 .pinmux_pins = dm646x_pins, 590 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), 591 .emac_pdata = &dm646x_emac_pdata, 592 .sram_dma = 0x10010000, 593 .sram_len = SZ_32K, 594}; 595 596void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) 597{ 598 dm646x_mcasp0_device.dev.platform_data = pdata; 599 platform_device_register(&dm646x_mcasp0_device); 600} 601 602void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) 603{ 604 dm646x_mcasp1_device.dev.platform_data = pdata; 605 platform_device_register(&dm646x_mcasp1_device); 606 platform_device_register(&dm646x_dit_device); 607} 608 609void dm646x_setup_vpif(struct vpif_display_config *display_config, 610 struct vpif_capture_config *capture_config) 611{ 612 unsigned int value; 613 614 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); 615 value &= ~VSCLKDIS_MASK; 616 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); 617 618 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); 619 value &= ~VDD3P3V_VID_MASK; 620 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); 621 622 davinci_cfg_reg(DM646X_STSOMUX_DISABLE); 623 davinci_cfg_reg(DM646X_STSIMUX_DISABLE); 624 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); 625 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); 626 627 vpif_display_dev.dev.platform_data = display_config; 628 vpif_capture_dev.dev.platform_data = capture_config; 629 platform_device_register(&vpif_dev); 630 platform_device_register(&vpif_display_dev); 631 platform_device_register(&vpif_capture_dev); 632} 633 634int __init dm646x_init_edma(struct edma_rsv_info *rsv) 635{ 636 struct platform_device *edma_pdev; 637 638 dm646x_edma_pdata.rsv = rsv; 639 640 edma_pdev = platform_device_register_full(&dm646x_edma_device); 641 return PTR_ERR_OR_ZERO(edma_pdev); 642} 643 644void __init dm646x_init(void) 645{ 646 davinci_common_init(&davinci_soc_info_dm646x); 647 davinci_map_sysmod(); 648} 649 650void __init dm646x_init_time(unsigned long ref_clk_rate, 651 unsigned long aux_clkin_rate) 652{ 653 void __iomem *pll1, *psc; 654 struct clk *clk; 655 int rv; 656 657 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); 658 clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); 659 660 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); 661 dm646x_pll1_init(NULL, pll1, NULL); 662 663 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); 664 dm646x_psc_init(NULL, psc); 665 666 clk = clk_get(NULL, "timer0"); 667 if (WARN_ON(IS_ERR(clk))) { 668 pr_err("Unable to get the timer clock\n"); 669 return; 670 } 671 672 rv = davinci_timer_register(clk, &dm646x_timer_cfg); 673 WARN(rv, "Unable to register the timer: %d\n", rv); 674} 675 676static struct resource dm646x_pll2_resources[] = { 677 { 678 .start = DAVINCI_PLL2_BASE, 679 .end = DAVINCI_PLL2_BASE + SZ_1K - 1, 680 .flags = IORESOURCE_MEM, 681 }, 682}; 683 684static struct platform_device dm646x_pll2_device = { 685 .name = "dm646x-pll2", 686 .id = -1, 687 .resource = dm646x_pll2_resources, 688 .num_resources = ARRAY_SIZE(dm646x_pll2_resources), 689}; 690 691void __init dm646x_register_clocks(void) 692{ 693 /* PLL1 and PSC are registered in dm646x_init_time() */ 694 platform_device_register(&dm646x_pll2_device); 695} 696 697static const struct davinci_aintc_config dm646x_aintc_config = { 698 .reg = { 699 .start = DAVINCI_ARM_INTC_BASE, 700 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, 701 .flags = IORESOURCE_MEM, 702 }, 703 .num_irqs = 64, 704 .prios = dm646x_default_priorities, 705}; 706 707void __init dm646x_init_irq(void) 708{ 709 davinci_aintc_init(&dm646x_aintc_config); 710} 711 712static int __init dm646x_init_devices(void) 713{ 714 int ret = 0; 715 716 if (!cpu_is_davinci_dm646x()) 717 return 0; 718 719 platform_device_register(&dm646x_mdio_device); 720 platform_device_register(&dm646x_emac_device); 721 722 ret = davinci_init_wdt(); 723 if (ret) 724 pr_warn("%s: watchdog init failed: %d\n", __func__, ret); 725 726 return ret; 727} 728postcore_initcall(dm646x_init_devices); 729