18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * TI DaVinci clock definitions 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2006-2007 Texas Instruments. 68c2ecf20Sopenharmony_ci * Copyright (C) 2008-2009 Deep Root Systems, LLC 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#ifndef __ARCH_ARM_DAVINCI_CLOCK_H 108c2ecf20Sopenharmony_ci#define __ARCH_ARM_DAVINCI_CLOCK_H 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/* PLL/Reset register offsets */ 138c2ecf20Sopenharmony_ci#define PLLCTL 0x100 148c2ecf20Sopenharmony_ci#define PLLCTL_PLLEN BIT(0) 158c2ecf20Sopenharmony_ci#define PLLCTL_PLLPWRDN BIT(1) 168c2ecf20Sopenharmony_ci#define PLLCTL_PLLRST BIT(3) 178c2ecf20Sopenharmony_ci#define PLLCTL_PLLDIS BIT(4) 188c2ecf20Sopenharmony_ci#define PLLCTL_PLLENSRC BIT(5) 198c2ecf20Sopenharmony_ci#define PLLCTL_CLKMODE BIT(8) 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#define PLLM 0x110 228c2ecf20Sopenharmony_ci#define PLLM_PLLM_MASK 0xff 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci#define PREDIV 0x114 258c2ecf20Sopenharmony_ci#define PLLDIV1 0x118 268c2ecf20Sopenharmony_ci#define PLLDIV2 0x11c 278c2ecf20Sopenharmony_ci#define PLLDIV3 0x120 288c2ecf20Sopenharmony_ci#define POSTDIV 0x128 298c2ecf20Sopenharmony_ci#define BPDIV 0x12c 308c2ecf20Sopenharmony_ci#define PLLCMD 0x138 318c2ecf20Sopenharmony_ci#define PLLSTAT 0x13c 328c2ecf20Sopenharmony_ci#define PLLALNCTL 0x140 338c2ecf20Sopenharmony_ci#define PLLDCHANGE 0x144 348c2ecf20Sopenharmony_ci#define PLLCKEN 0x148 358c2ecf20Sopenharmony_ci#define PLLCKSTAT 0x14c 368c2ecf20Sopenharmony_ci#define PLLSYSTAT 0x150 378c2ecf20Sopenharmony_ci#define PLLDIV4 0x160 388c2ecf20Sopenharmony_ci#define PLLDIV5 0x164 398c2ecf20Sopenharmony_ci#define PLLDIV6 0x168 408c2ecf20Sopenharmony_ci#define PLLDIV7 0x16c 418c2ecf20Sopenharmony_ci#define PLLDIV8 0x170 428c2ecf20Sopenharmony_ci#define PLLDIV9 0x174 438c2ecf20Sopenharmony_ci#define PLLDIV_EN BIT(15) 448c2ecf20Sopenharmony_ci#define PLLDIV_RATIO_MASK 0x1f 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci/* 478c2ecf20Sopenharmony_ci * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN 488c2ecf20Sopenharmony_ci * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us 498c2ecf20Sopenharmony_ci * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input 508c2ecf20Sopenharmony_ci * is ~25MHz. Units are micro seconds. 518c2ecf20Sopenharmony_ci */ 528c2ecf20Sopenharmony_ci#define PLL_BYPASS_TIME 1 538c2ecf20Sopenharmony_ci/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ 548c2ecf20Sopenharmony_ci#define PLL_RESET_TIME 1 558c2ecf20Sopenharmony_ci/* 568c2ecf20Sopenharmony_ci * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 578c2ecf20Sopenharmony_ci * Units are micro seconds. 588c2ecf20Sopenharmony_ci */ 598c2ecf20Sopenharmony_ci#define PLL_LOCK_TIME 20 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#endif 62