1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CNS3xxx common devices
4 *
5 * Copyright 2008 Cavium Networks
6 *		  Scott Shu
7 * Copyright 2010 MontaVista Software, LLC.
8 *		  Anton Vorontsov <avorontsov@mvista.com>
9 */
10
11#include <linux/io.h>
12#include <linux/init.h>
13#include <linux/compiler.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include "cns3xxx.h"
17#include "pm.h"
18#include "core.h"
19#include "devices.h"
20
21/*
22 * AHCI
23 */
24static struct resource cns3xxx_ahci_resource[] = {
25	[0] = {
26		.start	= CNS3XXX_SATA2_BASE,
27		.end	= CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
28		.flags	= IORESOURCE_MEM,
29	},
30	[1] = {
31		.start	= IRQ_CNS3XXX_SATA,
32		.end	= IRQ_CNS3XXX_SATA,
33		.flags	= IORESOURCE_IRQ,
34	},
35};
36
37static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
38
39static struct platform_device cns3xxx_ahci_pdev = {
40	.name		= "ahci",
41	.id		= 0,
42	.resource	= cns3xxx_ahci_resource,
43	.num_resources	= ARRAY_SIZE(cns3xxx_ahci_resource),
44	.dev		= {
45		.dma_mask		= &cns3xxx_ahci_dmamask,
46		.coherent_dma_mask	= DMA_BIT_MASK(32),
47	},
48};
49
50void __init cns3xxx_ahci_init(void)
51{
52	u32 tmp;
53
54	tmp = __raw_readl(MISC_SATA_POWER_MODE);
55	tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
56	tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
57	__raw_writel(tmp, MISC_SATA_POWER_MODE);
58
59	/* Enable SATA PHY */
60	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
61	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
62
63	/* Enable SATA Clock */
64	cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
65
66	/* De-Asscer SATA Reset */
67	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
68
69	platform_device_register(&cns3xxx_ahci_pdev);
70}
71
72/*
73 * SDHCI
74 */
75static struct resource cns3xxx_sdhci_resources[] = {
76	[0] = {
77		.start = CNS3XXX_SDIO_BASE,
78		.end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
79		.flags = IORESOURCE_MEM,
80	},
81	[1] = {
82		.start = IRQ_CNS3XXX_SDIO,
83		.end   = IRQ_CNS3XXX_SDIO,
84		.flags = IORESOURCE_IRQ,
85	},
86};
87
88static struct platform_device cns3xxx_sdhci_pdev = {
89	.name		= "sdhci-cns3xxx",
90	.id		= 0,
91	.num_resources	= ARRAY_SIZE(cns3xxx_sdhci_resources),
92	.resource	= cns3xxx_sdhci_resources,
93};
94
95void __init cns3xxx_sdhci_init(void)
96{
97	u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
98	u32 gpioa_pins = __raw_readl(gpioa);
99
100	/* MMC/SD pins share with GPIOA */
101	gpioa_pins |= 0x1fff0004;
102	__raw_writel(gpioa_pins, gpioa);
103
104	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
105	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
106
107	platform_device_register(&cns3xxx_sdhci_pdev);
108}
109