18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2012 Linaro Limited. 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef VIRT_H 78c2ecf20Sopenharmony_ci#define VIRT_H 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include <asm/ptrace.h> 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* 128c2ecf20Sopenharmony_ci * Flag indicating that the kernel was not entered in the same mode on every 138c2ecf20Sopenharmony_ci * CPU. The zImage loader stashes this value in an SPSR, so we need an 148c2ecf20Sopenharmony_ci * architecturally defined flag bit here. 158c2ecf20Sopenharmony_ci */ 168c2ecf20Sopenharmony_ci#define BOOT_CPU_MODE_MISMATCH PSR_N_BIT 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci#ifndef __ASSEMBLY__ 198c2ecf20Sopenharmony_ci#include <asm/cacheflush.h> 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#ifdef CONFIG_ARM_VIRT_EXT 228c2ecf20Sopenharmony_ci/* 238c2ecf20Sopenharmony_ci * __boot_cpu_mode records what mode the primary CPU was booted in. 248c2ecf20Sopenharmony_ci * A correctly-implemented bootloader must start all CPUs in the same mode: 258c2ecf20Sopenharmony_ci * if it fails to do this, the flag BOOT_CPU_MODE_MISMATCH is set to indicate 268c2ecf20Sopenharmony_ci * that some CPU(s) were booted in a different mode. 278c2ecf20Sopenharmony_ci * 288c2ecf20Sopenharmony_ci * This allows the kernel to flag an error when the secondaries have come up. 298c2ecf20Sopenharmony_ci */ 308c2ecf20Sopenharmony_ciextern int __boot_cpu_mode; 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_cistatic inline void sync_boot_mode(void) 338c2ecf20Sopenharmony_ci{ 348c2ecf20Sopenharmony_ci /* 358c2ecf20Sopenharmony_ci * As secondaries write to __boot_cpu_mode with caches disabled, we 368c2ecf20Sopenharmony_ci * must flush the corresponding cache entries to ensure the visibility 378c2ecf20Sopenharmony_ci * of their writes. 388c2ecf20Sopenharmony_ci */ 398c2ecf20Sopenharmony_ci sync_cache_r(&__boot_cpu_mode); 408c2ecf20Sopenharmony_ci} 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci#else 438c2ecf20Sopenharmony_ci#define __boot_cpu_mode (SVC_MODE) 448c2ecf20Sopenharmony_ci#define sync_boot_mode() 458c2ecf20Sopenharmony_ci#endif 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci#ifndef ZIMAGE 488c2ecf20Sopenharmony_civoid hyp_mode_check(void); 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci/* Reports the availability of HYP mode */ 518c2ecf20Sopenharmony_cistatic inline bool is_hyp_mode_available(void) 528c2ecf20Sopenharmony_ci{ 538c2ecf20Sopenharmony_ci return ((__boot_cpu_mode & MODE_MASK) == HYP_MODE && 548c2ecf20Sopenharmony_ci !(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH)); 558c2ecf20Sopenharmony_ci} 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci/* Check if the bootloader has booted CPUs in different modes */ 588c2ecf20Sopenharmony_cistatic inline bool is_hyp_mode_mismatched(void) 598c2ecf20Sopenharmony_ci{ 608c2ecf20Sopenharmony_ci return !!(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH); 618c2ecf20Sopenharmony_ci} 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_cistatic inline bool is_kernel_in_hyp_mode(void) 648c2ecf20Sopenharmony_ci{ 658c2ecf20Sopenharmony_ci return false; 668c2ecf20Sopenharmony_ci} 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci#endif 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci#else 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci/* Only assembly code should need those */ 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ci#define HVC_SET_VECTORS 0 758c2ecf20Sopenharmony_ci#define HVC_SOFT_RESTART 1 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_ci#endif /* __ASSEMBLY__ */ 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci#define HVC_STUB_ERR 0xbadca11 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_ci#endif /* ! VIRT_H */ 82