18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * arch/arm/include/asm/cache.h 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci#ifndef __ASMARM_CACHE_H 68c2ecf20Sopenharmony_ci#define __ASMARM_CACHE_H 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT 98c2ecf20Sopenharmony_ci#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* 128c2ecf20Sopenharmony_ci * Memory returned by kmalloc() may be used for DMA, so we must make 138c2ecf20Sopenharmony_ci * sure that all such allocations are cache aligned. Otherwise, 148c2ecf20Sopenharmony_ci * unrelated code may cause parts of the buffer to be read into the 158c2ecf20Sopenharmony_ci * cache before the transfer is done, causing old data to be seen by 168c2ecf20Sopenharmony_ci * the CPU. 178c2ecf20Sopenharmony_ci */ 188c2ecf20Sopenharmony_ci#define ARCH_DMA_MINALIGN L1_CACHE_BYTES 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci/* 218c2ecf20Sopenharmony_ci * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. 228c2ecf20Sopenharmony_ci */ 238c2ecf20Sopenharmony_ci#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 248c2ecf20Sopenharmony_ci#define ARCH_SLAB_MINALIGN 8 258c2ecf20Sopenharmony_ci#endif 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci#define __read_mostly __section(".data..read_mostly") 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci#endif 30