18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2020 Marek Vasut <marex@denx.de> 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#include <dt-bindings/input/input.h> 78c2ecf20Sopenharmony_ci#include <dt-bindings/pwm/pwm.h> 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci/ { 108c2ecf20Sopenharmony_ci aliases { 118c2ecf20Sopenharmony_ci serial0 = &uart4; 128c2ecf20Sopenharmony_ci serial1 = &usart3; 138c2ecf20Sopenharmony_ci serial2 = &uart8; 148c2ecf20Sopenharmony_ci }; 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci chosen { 178c2ecf20Sopenharmony_ci stdout-path = "serial0:115200n8"; 188c2ecf20Sopenharmony_ci }; 198c2ecf20Sopenharmony_ci}; 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci&adc { 228c2ecf20Sopenharmony_ci status = "disabled"; 238c2ecf20Sopenharmony_ci}; 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci&dac { 268c2ecf20Sopenharmony_ci status = "disabled"; 278c2ecf20Sopenharmony_ci}; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci&gpiob { 308c2ecf20Sopenharmony_ci /* 318c2ecf20Sopenharmony_ci * NOTE: On DRC02, the RS485_RX_En is controlled by a separate 328c2ecf20Sopenharmony_ci * GPIO line, however the STM32 UART driver assumes RX happens 338c2ecf20Sopenharmony_ci * during TX anyway and that it only controls drive enable DE 348c2ecf20Sopenharmony_ci * line. Hence, the RX is always enabled here. 358c2ecf20Sopenharmony_ci */ 368c2ecf20Sopenharmony_ci rs485-rx-en { 378c2ecf20Sopenharmony_ci gpio-hog; 388c2ecf20Sopenharmony_ci gpios = <8 0>; 398c2ecf20Sopenharmony_ci output-low; 408c2ecf20Sopenharmony_ci line-name = "rs485-rx-en"; 418c2ecf20Sopenharmony_ci }; 428c2ecf20Sopenharmony_ci}; 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci&gpiod { 458c2ecf20Sopenharmony_ci gpio-line-names = "", "", "", "", 468c2ecf20Sopenharmony_ci "", "", "", "", 478c2ecf20Sopenharmony_ci "", "", "", "Out1", 488c2ecf20Sopenharmony_ci "Out2", "", "", ""; 498c2ecf20Sopenharmony_ci}; 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci&gpioi { 528c2ecf20Sopenharmony_ci gpio-line-names = "In1", "", "", "", 538c2ecf20Sopenharmony_ci "", "", "", "", 548c2ecf20Sopenharmony_ci "In2", "", "", "", 558c2ecf20Sopenharmony_ci "", "", "", ""; 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci /* 588c2ecf20Sopenharmony_ci * NOTE: The USB Hub on the DRC02 needs a reset signal to be 598c2ecf20Sopenharmony_ci * pulled high in order to be detected by the USB Controller. 608c2ecf20Sopenharmony_ci * This signal should be handled by USB power sequencing in 618c2ecf20Sopenharmony_ci * order to reset the Hub when USB bus is powered down, but 628c2ecf20Sopenharmony_ci * so far there is no such functionality. 638c2ecf20Sopenharmony_ci */ 648c2ecf20Sopenharmony_ci usb-hub { 658c2ecf20Sopenharmony_ci gpio-hog; 668c2ecf20Sopenharmony_ci gpios = <2 0>; 678c2ecf20Sopenharmony_ci output-high; 688c2ecf20Sopenharmony_ci line-name = "usb-hub-reset"; 698c2ecf20Sopenharmony_ci }; 708c2ecf20Sopenharmony_ci}; 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci&i2c2 { 738c2ecf20Sopenharmony_ci pinctrl-names = "default"; 748c2ecf20Sopenharmony_ci pinctrl-0 = <&i2c2_pins_a>; 758c2ecf20Sopenharmony_ci i2c-scl-rising-time-ns = <185>; 768c2ecf20Sopenharmony_ci i2c-scl-falling-time-ns = <20>; 778c2ecf20Sopenharmony_ci status = "okay"; 788c2ecf20Sopenharmony_ci /* spare dmas for other usage */ 798c2ecf20Sopenharmony_ci /delete-property/dmas; 808c2ecf20Sopenharmony_ci /delete-property/dma-names; 818c2ecf20Sopenharmony_ci status = "okay"; 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci eeprom@50 { 848c2ecf20Sopenharmony_ci compatible = "atmel,24c04"; 858c2ecf20Sopenharmony_ci reg = <0x50>; 868c2ecf20Sopenharmony_ci pagesize = <16>; 878c2ecf20Sopenharmony_ci }; 888c2ecf20Sopenharmony_ci}; 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ci&i2c4 { 918c2ecf20Sopenharmony_ci touchscreen@49 { 928c2ecf20Sopenharmony_ci status = "disabled"; 938c2ecf20Sopenharmony_ci }; 948c2ecf20Sopenharmony_ci}; 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci&i2c5 { /* TP7/TP8 */ 978c2ecf20Sopenharmony_ci pinctrl-names = "default"; 988c2ecf20Sopenharmony_ci pinctrl-0 = <&i2c5_pins_a>; 998c2ecf20Sopenharmony_ci i2c-scl-rising-time-ns = <185>; 1008c2ecf20Sopenharmony_ci i2c-scl-falling-time-ns = <20>; 1018c2ecf20Sopenharmony_ci status = "okay"; 1028c2ecf20Sopenharmony_ci /* spare dmas for other usage */ 1038c2ecf20Sopenharmony_ci /delete-property/dmas; 1048c2ecf20Sopenharmony_ci /delete-property/dma-names; 1058c2ecf20Sopenharmony_ci}; 1068c2ecf20Sopenharmony_ci 1078c2ecf20Sopenharmony_ci&sdmmc3 { 1088c2ecf20Sopenharmony_ci /* 1098c2ecf20Sopenharmony_ci * On DRC02, the SoM does not have SDIO WiFi. The pins 1108c2ecf20Sopenharmony_ci * are used for on-board microSD slot instead. 1118c2ecf20Sopenharmony_ci */ 1128c2ecf20Sopenharmony_ci /delete-property/broken-cd; 1138c2ecf20Sopenharmony_ci cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; 1148c2ecf20Sopenharmony_ci disable-wp; 1158c2ecf20Sopenharmony_ci}; 1168c2ecf20Sopenharmony_ci 1178c2ecf20Sopenharmony_ci&spi1 { 1188c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1198c2ecf20Sopenharmony_ci pinctrl-0 = <&spi1_pins_a>; 1208c2ecf20Sopenharmony_ci cs-gpios = <&gpioz 3 0>; 1218c2ecf20Sopenharmony_ci /* Use PIO for the display */ 1228c2ecf20Sopenharmony_ci /delete-property/dmas; 1238c2ecf20Sopenharmony_ci /delete-property/dma-names; 1248c2ecf20Sopenharmony_ci status = "disabled"; /* Enable once there is display driver */ 1258c2ecf20Sopenharmony_ci /* 1268c2ecf20Sopenharmony_ci * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are 1278c2ecf20Sopenharmony_ci * also connected to the display board connector. 1288c2ecf20Sopenharmony_ci */ 1298c2ecf20Sopenharmony_ci}; 1308c2ecf20Sopenharmony_ci 1318c2ecf20Sopenharmony_ci&usart3 { 1328c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1338c2ecf20Sopenharmony_ci pinctrl-0 = <&usart3_pins_a>; 1348c2ecf20Sopenharmony_ci status = "okay"; 1358c2ecf20Sopenharmony_ci}; 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_ci/* 1388c2ecf20Sopenharmony_ci * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), 1398c2ecf20Sopenharmony_ci * however the STM32MP1 pinmux cannot map them to UART4 . 1408c2ecf20Sopenharmony_ci */ 1418c2ecf20Sopenharmony_ci 1428c2ecf20Sopenharmony_ci&uart8 { /* RS485 */ 1438c2ecf20Sopenharmony_ci linux,rs485-enabled-at-boot-time; 1448c2ecf20Sopenharmony_ci pinctrl-names = "default"; 1458c2ecf20Sopenharmony_ci pinctrl-0 = <&uart8_pins_a>; 1468c2ecf20Sopenharmony_ci rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; 1478c2ecf20Sopenharmony_ci status = "okay"; 1488c2ecf20Sopenharmony_ci}; 1498c2ecf20Sopenharmony_ci 1508c2ecf20Sopenharmony_ci&usbh_ehci { 1518c2ecf20Sopenharmony_ci phys = <&usbphyc_port0>; 1528c2ecf20Sopenharmony_ci status = "okay"; 1538c2ecf20Sopenharmony_ci}; 1548c2ecf20Sopenharmony_ci 1558c2ecf20Sopenharmony_ci&usbphyc { 1568c2ecf20Sopenharmony_ci status = "okay"; 1578c2ecf20Sopenharmony_ci}; 1588c2ecf20Sopenharmony_ci 1598c2ecf20Sopenharmony_ci&usbphyc_port0 { 1608c2ecf20Sopenharmony_ci phy-supply = <&vdd_usb>; 1618c2ecf20Sopenharmony_ci vdda1v1-supply = <®11>; 1628c2ecf20Sopenharmony_ci vdda1v8-supply = <®18>; 1638c2ecf20Sopenharmony_ci}; 164