1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 #address-cells = <2>; 53 #size-cells = <2>; 54 compatible = "fsl,ls1021a"; 55 interrupt-parent = <&gic>; 56 57 aliases { 58 crypto = &crypto; 59 ethernet0 = &enet0; 60 ethernet1 = &enet1; 61 ethernet2 = &enet2; 62 rtc1 = &ftm_alarm0; 63 serial0 = &lpuart0; 64 serial1 = &lpuart1; 65 serial2 = &lpuart2; 66 serial3 = &lpuart3; 67 serial4 = &lpuart4; 68 serial5 = &lpuart5; 69 sysclk = &sysclk; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu0: cpu@f00 { 77 compatible = "arm,cortex-a7"; 78 device_type = "cpu"; 79 reg = <0xf00>; 80 clocks = <&clockgen 1 0>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu1: cpu@f01 { 85 compatible = "arm,cortex-a7"; 86 device_type = "cpu"; 87 reg = <0xf01>; 88 clocks = <&clockgen 1 0>; 89 #cooling-cells = <2>; 90 }; 91 }; 92 93 memory { 94 device_type = "memory"; 95 reg = <0x0 0x0 0x0 0x0>; 96 }; 97 98 sysclk: sysclk { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <100000000>; 102 clock-output-names = "sysclk"; 103 }; 104 105 timer { 106 compatible = "arm,armv7-timer"; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 108 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 110 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 111 }; 112 113 pmu { 114 compatible = "arm,cortex-a7-pmu"; 115 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 117 interrupt-affinity = <&cpu0>, <&cpu1>; 118 }; 119 120 reboot { 121 compatible = "syscon-reboot"; 122 regmap = <&dcfg>; 123 offset = <0xb0>; 124 mask = <0x02>; 125 }; 126 127 soc { 128 compatible = "simple-bus"; 129 #address-cells = <2>; 130 #size-cells = <2>; 131 device_type = "soc"; 132 interrupt-parent = <&gic>; 133 ranges; 134 135 ddr: memory-controller@1080000 { 136 compatible = "fsl,qoriq-memory-controller"; 137 reg = <0x0 0x1080000 0x0 0x1000>; 138 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 139 big-endian; 140 }; 141 142 gic: interrupt-controller@1400000 { 143 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 144 #interrupt-cells = <3>; 145 interrupt-controller; 146 reg = <0x0 0x1401000 0x0 0x1000>, 147 <0x0 0x1402000 0x0 0x2000>, 148 <0x0 0x1404000 0x0 0x2000>, 149 <0x0 0x1406000 0x0 0x2000>; 150 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 151 152 }; 153 154 msi1: msi-controller@1570e00 { 155 compatible = "fsl,ls1021a-msi"; 156 reg = <0x0 0x1570e00 0x0 0x8>; 157 msi-controller; 158 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 159 }; 160 161 msi2: msi-controller@1570e08 { 162 compatible = "fsl,ls1021a-msi"; 163 reg = <0x0 0x1570e08 0x0 0x8>; 164 msi-controller; 165 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 168 ifc: ifc@1530000 { 169 compatible = "fsl,ifc", "simple-bus"; 170 reg = <0x0 0x1530000 0x0 0x10000>; 171 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 172 }; 173 174 dcfg: dcfg@1ee0000 { 175 compatible = "fsl,ls1021a-dcfg", "syscon"; 176 reg = <0x0 0x1ee0000 0x0 0x10000>; 177 big-endian; 178 }; 179 180 qspi: spi@1550000 { 181 compatible = "fsl,ls1021a-qspi"; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 reg = <0x0 0x1550000 0x0 0x10000>, 185 <0x0 0x40000000 0x0 0x20000000>; 186 reg-names = "QuadSPI", "QuadSPI-memory"; 187 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 188 clock-names = "qspi_en", "qspi"; 189 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 190 status = "disabled"; 191 }; 192 193 esdhc: esdhc@1560000 { 194 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; 195 reg = <0x0 0x1560000 0x0 0x10000>; 196 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 197 clock-frequency = <0>; 198 voltage-ranges = <1800 1800 3300 3300>; 199 sdhci,auto-cmd12; 200 big-endian; 201 bus-width = <4>; 202 status = "disabled"; 203 }; 204 205 sata: sata@3200000 { 206 compatible = "fsl,ls1021a-ahci"; 207 reg = <0x0 0x3200000 0x0 0x10000>, 208 <0x0 0x20220520 0x0 0x4>; 209 reg-names = "ahci", "sata-ecc"; 210 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&clockgen 4 1>; 212 dma-coherent; 213 status = "disabled"; 214 }; 215 216 scfg: scfg@1570000 { 217 compatible = "fsl,ls1021a-scfg", "syscon"; 218 reg = <0x0 0x1570000 0x0 0x10000>; 219 big-endian; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 ranges = <0x0 0x0 0x1570000 0x10000>; 223 224 extirq: interrupt-controller@1ac { 225 compatible = "fsl,ls1021a-extirq"; 226 #interrupt-cells = <2>; 227 #address-cells = <0>; 228 interrupt-controller; 229 reg = <0x1ac 4>; 230 interrupt-map = 231 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 232 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 233 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 234 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 235 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 236 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-map-mask = <0xffffffff 0x0>; 238 }; 239 }; 240 241 crypto: crypto@1700000 { 242 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 243 fsl,sec-era = <7>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 reg = <0x0 0x1700000 0x0 0x100000>; 247 ranges = <0x0 0x0 0x1700000 0x100000>; 248 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 249 250 sec_jr0: jr@10000 { 251 compatible = "fsl,sec-v5.0-job-ring", 252 "fsl,sec-v4.0-job-ring"; 253 reg = <0x10000 0x10000>; 254 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 255 }; 256 257 sec_jr1: jr@20000 { 258 compatible = "fsl,sec-v5.0-job-ring", 259 "fsl,sec-v4.0-job-ring"; 260 reg = <0x20000 0x10000>; 261 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 264 sec_jr2: jr@30000 { 265 compatible = "fsl,sec-v5.0-job-ring", 266 "fsl,sec-v4.0-job-ring"; 267 reg = <0x30000 0x10000>; 268 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 269 }; 270 271 sec_jr3: jr@40000 { 272 compatible = "fsl,sec-v5.0-job-ring", 273 "fsl,sec-v4.0-job-ring"; 274 reg = <0x40000 0x10000>; 275 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 }; 279 280 clockgen: clocking@1ee1000 { 281 compatible = "fsl,ls1021a-clockgen"; 282 reg = <0x0 0x1ee1000 0x0 0x1000>; 283 #clock-cells = <2>; 284 clocks = <&sysclk>; 285 }; 286 287 tmu: tmu@1f00000 { 288 compatible = "fsl,qoriq-tmu"; 289 reg = <0x0 0x1f00000 0x0 0x10000>; 290 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 291 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; 292 fsl,tmu-calibration = <0x00000000 0x0000000f 293 0x00000001 0x00000017 294 0x00000002 0x0000001e 295 0x00000003 0x00000026 296 0x00000004 0x0000002e 297 0x00000005 0x00000035 298 0x00000006 0x0000003d 299 0x00000007 0x00000044 300 0x00000008 0x0000004c 301 0x00000009 0x00000053 302 0x0000000a 0x0000005b 303 0x0000000b 0x00000064 304 305 0x00010000 0x00000011 306 0x00010001 0x0000001c 307 0x00010002 0x00000024 308 0x00010003 0x0000002b 309 0x00010004 0x00000034 310 0x00010005 0x00000039 311 0x00010006 0x00000042 312 0x00010007 0x0000004c 313 0x00010008 0x00000051 314 0x00010009 0x0000005a 315 0x0001000a 0x00000063 316 317 0x00020000 0x00000013 318 0x00020001 0x00000019 319 0x00020002 0x00000024 320 0x00020003 0x0000002c 321 0x00020004 0x00000035 322 0x00020005 0x0000003d 323 0x00020006 0x00000046 324 0x00020007 0x00000050 325 0x00020008 0x00000059 326 327 0x00030000 0x00000002 328 0x00030001 0x0000000d 329 0x00030002 0x00000019 330 0x00030003 0x00000024>; 331 #thermal-sensor-cells = <1>; 332 }; 333 334 dspi0: spi@2100000 { 335 compatible = "fsl,ls1021a-v1.0-dspi"; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 reg = <0x0 0x2100000 0x0 0x10000>; 339 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 340 clock-names = "dspi"; 341 clocks = <&clockgen 4 1>; 342 spi-num-chipselects = <6>; 343 big-endian; 344 status = "disabled"; 345 }; 346 347 dspi1: spi@2110000 { 348 compatible = "fsl,ls1021a-v1.0-dspi"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 reg = <0x0 0x2110000 0x0 0x10000>; 352 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 353 clock-names = "dspi"; 354 clocks = <&clockgen 4 1>; 355 spi-num-chipselects = <6>; 356 big-endian; 357 status = "disabled"; 358 }; 359 360 i2c0: i2c@2180000 { 361 compatible = "fsl,vf610-i2c"; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 reg = <0x0 0x2180000 0x0 0x10000>; 365 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 366 clock-names = "i2c"; 367 clocks = <&clockgen 4 1>; 368 dma-names = "tx", "rx"; 369 dmas = <&edma0 1 39>, <&edma0 1 38>; 370 status = "disabled"; 371 }; 372 373 i2c1: i2c@2190000 { 374 compatible = "fsl,vf610-i2c"; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 reg = <0x0 0x2190000 0x0 0x10000>; 378 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 379 clock-names = "i2c"; 380 clocks = <&clockgen 4 1>; 381 dma-names = "tx", "rx"; 382 dmas = <&edma0 1 37>, <&edma0 1 36>; 383 status = "disabled"; 384 }; 385 386 i2c2: i2c@21a0000 { 387 compatible = "fsl,vf610-i2c"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <0x0 0x21a0000 0x0 0x10000>; 391 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 392 clock-names = "i2c"; 393 clocks = <&clockgen 4 1>; 394 dma-names = "tx", "rx"; 395 dmas = <&edma0 1 35>, <&edma0 1 34>; 396 status = "disabled"; 397 }; 398 399 uart0: serial@21c0500 { 400 compatible = "fsl,16550-FIFO64", "ns16550a"; 401 reg = <0x0 0x21c0500 0x0 0x100>; 402 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 403 clock-frequency = <0>; 404 fifo-size = <15>; 405 status = "disabled"; 406 }; 407 408 uart1: serial@21c0600 { 409 compatible = "fsl,16550-FIFO64", "ns16550a"; 410 reg = <0x0 0x21c0600 0x0 0x100>; 411 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 412 clock-frequency = <0>; 413 fifo-size = <15>; 414 status = "disabled"; 415 }; 416 417 uart2: serial@21d0500 { 418 compatible = "fsl,16550-FIFO64", "ns16550a"; 419 reg = <0x0 0x21d0500 0x0 0x100>; 420 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <0>; 422 fifo-size = <15>; 423 status = "disabled"; 424 }; 425 426 uart3: serial@21d0600 { 427 compatible = "fsl,16550-FIFO64", "ns16550a"; 428 reg = <0x0 0x21d0600 0x0 0x100>; 429 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 430 clock-frequency = <0>; 431 fifo-size = <15>; 432 status = "disabled"; 433 }; 434 435 counter0: counter@29d0000 { 436 compatible = "fsl,ftm-quaddec"; 437 reg = <0x0 0x29d0000 0x0 0x10000>; 438 big-endian; 439 status = "disabled"; 440 }; 441 442 counter1: counter@29e0000 { 443 compatible = "fsl,ftm-quaddec"; 444 reg = <0x0 0x29e0000 0x0 0x10000>; 445 big-endian; 446 status = "disabled"; 447 }; 448 449 counter2: counter@29f0000 { 450 compatible = "fsl,ftm-quaddec"; 451 reg = <0x0 0x29f0000 0x0 0x10000>; 452 big-endian; 453 status = "disabled"; 454 }; 455 456 counter3: counter@2a00000 { 457 compatible = "fsl,ftm-quaddec"; 458 reg = <0x0 0x2a00000 0x0 0x10000>; 459 big-endian; 460 status = "disabled"; 461 }; 462 463 gpio0: gpio@2300000 { 464 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 465 reg = <0x0 0x2300000 0x0 0x10000>; 466 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 }; 472 473 gpio1: gpio@2310000 { 474 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 475 reg = <0x0 0x2310000 0x0 0x10000>; 476 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 }; 482 483 gpio2: gpio@2320000 { 484 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 485 reg = <0x0 0x2320000 0x0 0x10000>; 486 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 487 gpio-controller; 488 #gpio-cells = <2>; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 }; 492 493 gpio3: gpio@2330000 { 494 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 495 reg = <0x0 0x2330000 0x0 0x10000>; 496 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 }; 502 503 lpuart0: serial@2950000 { 504 compatible = "fsl,ls1021a-lpuart"; 505 reg = <0x0 0x2950000 0x0 0x1000>; 506 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&sysclk>; 508 clock-names = "ipg"; 509 status = "disabled"; 510 }; 511 512 lpuart1: serial@2960000 { 513 compatible = "fsl,ls1021a-lpuart"; 514 reg = <0x0 0x2960000 0x0 0x1000>; 515 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clockgen 4 1>; 517 clock-names = "ipg"; 518 status = "disabled"; 519 }; 520 521 lpuart2: serial@2970000 { 522 compatible = "fsl,ls1021a-lpuart"; 523 reg = <0x0 0x2970000 0x0 0x1000>; 524 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clockgen 4 1>; 526 clock-names = "ipg"; 527 status = "disabled"; 528 }; 529 530 lpuart3: serial@2980000 { 531 compatible = "fsl,ls1021a-lpuart"; 532 reg = <0x0 0x2980000 0x0 0x1000>; 533 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clockgen 4 1>; 535 clock-names = "ipg"; 536 status = "disabled"; 537 }; 538 539 lpuart4: serial@2990000 { 540 compatible = "fsl,ls1021a-lpuart"; 541 reg = <0x0 0x2990000 0x0 0x1000>; 542 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clockgen 4 1>; 544 clock-names = "ipg"; 545 status = "disabled"; 546 }; 547 548 lpuart5: serial@29a0000 { 549 compatible = "fsl,ls1021a-lpuart"; 550 reg = <0x0 0x29a0000 0x0 0x1000>; 551 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clockgen 4 1>; 553 clock-names = "ipg"; 554 status = "disabled"; 555 }; 556 557 pwm0: pwm@29d0000 { 558 compatible = "fsl,vf610-ftm-pwm"; 559 #pwm-cells = <3>; 560 reg = <0x0 0x29d0000 0x0 0x10000>; 561 clock-names = "ftm_sys", "ftm_ext", 562 "ftm_fix", "ftm_cnt_clk_en"; 563 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 564 <&clockgen 4 1>, <&clockgen 4 1>; 565 big-endian; 566 status = "disabled"; 567 }; 568 569 pwm1: pwm@29e0000 { 570 compatible = "fsl,vf610-ftm-pwm"; 571 #pwm-cells = <3>; 572 reg = <0x0 0x29e0000 0x0 0x10000>; 573 clock-names = "ftm_sys", "ftm_ext", 574 "ftm_fix", "ftm_cnt_clk_en"; 575 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 576 <&clockgen 4 1>, <&clockgen 4 1>; 577 big-endian; 578 status = "disabled"; 579 }; 580 581 pwm2: pwm@29f0000 { 582 compatible = "fsl,vf610-ftm-pwm"; 583 #pwm-cells = <3>; 584 reg = <0x0 0x29f0000 0x0 0x10000>; 585 clock-names = "ftm_sys", "ftm_ext", 586 "ftm_fix", "ftm_cnt_clk_en"; 587 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 588 <&clockgen 4 1>, <&clockgen 4 1>; 589 big-endian; 590 status = "disabled"; 591 }; 592 593 pwm3: pwm@2a00000 { 594 compatible = "fsl,vf610-ftm-pwm"; 595 #pwm-cells = <3>; 596 reg = <0x0 0x2a00000 0x0 0x10000>; 597 clock-names = "ftm_sys", "ftm_ext", 598 "ftm_fix", "ftm_cnt_clk_en"; 599 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 600 <&clockgen 4 1>, <&clockgen 4 1>; 601 big-endian; 602 status = "disabled"; 603 }; 604 605 pwm4: pwm@2a10000 { 606 compatible = "fsl,vf610-ftm-pwm"; 607 #pwm-cells = <3>; 608 reg = <0x0 0x2a10000 0x0 0x10000>; 609 clock-names = "ftm_sys", "ftm_ext", 610 "ftm_fix", "ftm_cnt_clk_en"; 611 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 612 <&clockgen 4 1>, <&clockgen 4 1>; 613 big-endian; 614 status = "disabled"; 615 }; 616 617 pwm5: pwm@2a20000 { 618 compatible = "fsl,vf610-ftm-pwm"; 619 #pwm-cells = <3>; 620 reg = <0x0 0x2a20000 0x0 0x10000>; 621 clock-names = "ftm_sys", "ftm_ext", 622 "ftm_fix", "ftm_cnt_clk_en"; 623 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 624 <&clockgen 4 1>, <&clockgen 4 1>; 625 big-endian; 626 status = "disabled"; 627 }; 628 629 pwm6: pwm@2a30000 { 630 compatible = "fsl,vf610-ftm-pwm"; 631 #pwm-cells = <3>; 632 reg = <0x0 0x2a30000 0x0 0x10000>; 633 clock-names = "ftm_sys", "ftm_ext", 634 "ftm_fix", "ftm_cnt_clk_en"; 635 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 636 <&clockgen 4 1>, <&clockgen 4 1>; 637 big-endian; 638 status = "disabled"; 639 }; 640 641 pwm7: pwm@2a40000 { 642 compatible = "fsl,vf610-ftm-pwm"; 643 #pwm-cells = <3>; 644 reg = <0x0 0x2a40000 0x0 0x10000>; 645 clock-names = "ftm_sys", "ftm_ext", 646 "ftm_fix", "ftm_cnt_clk_en"; 647 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 648 <&clockgen 4 1>, <&clockgen 4 1>; 649 big-endian; 650 status = "disabled"; 651 }; 652 653 wdog0: watchdog@2ad0000 { 654 compatible = "fsl,imx21-wdt"; 655 reg = <0x0 0x2ad0000 0x0 0x10000>; 656 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&clockgen 4 1>; 658 clock-names = "wdog-en"; 659 big-endian; 660 }; 661 662 sai1: sai@2b50000 { 663 #sound-dai-cells = <0>; 664 compatible = "fsl,vf610-sai"; 665 reg = <0x0 0x2b50000 0x0 0x10000>; 666 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 668 <&clockgen 4 1>, <&clockgen 4 1>; 669 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 670 dma-names = "tx", "rx"; 671 dmas = <&edma0 1 47>, 672 <&edma0 1 46>; 673 status = "disabled"; 674 }; 675 676 sai2: sai@2b60000 { 677 #sound-dai-cells = <0>; 678 compatible = "fsl,vf610-sai"; 679 reg = <0x0 0x2b60000 0x0 0x10000>; 680 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 682 <&clockgen 4 1>, <&clockgen 4 1>; 683 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 684 dma-names = "tx", "rx"; 685 dmas = <&edma0 1 45>, 686 <&edma0 1 44>; 687 status = "disabled"; 688 }; 689 690 edma0: edma@2c00000 { 691 #dma-cells = <2>; 692 compatible = "fsl,vf610-edma"; 693 reg = <0x0 0x2c00000 0x0 0x10000>, 694 <0x0 0x2c10000 0x0 0x10000>, 695 <0x0 0x2c20000 0x0 0x10000>; 696 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 698 interrupt-names = "edma-tx", "edma-err"; 699 dma-channels = <32>; 700 big-endian; 701 clock-names = "dmamux0", "dmamux1"; 702 clocks = <&clockgen 4 1>, 703 <&clockgen 4 1>; 704 }; 705 706 dcu: dcu@2ce0000 { 707 compatible = "fsl,ls1021a-dcu"; 708 reg = <0x0 0x2ce0000 0x0 0x10000>; 709 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&clockgen 4 0>, 711 <&clockgen 4 0>; 712 clock-names = "dcu", "pix"; 713 big-endian; 714 status = "disabled"; 715 }; 716 717 mdio0: mdio@2d24000 { 718 compatible = "gianfar"; 719 device_type = "mdio"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 reg = <0x0 0x2d24000 0x0 0x4000>, 723 <0x0 0x2d10030 0x0 0x4>; 724 }; 725 726 mdio1: mdio@2d64000 { 727 compatible = "gianfar"; 728 device_type = "mdio"; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 reg = <0x0 0x2d64000 0x0 0x4000>, 732 <0x0 0x2d50030 0x0 0x4>; 733 }; 734 735 ptp_clock@2d10e00 { 736 compatible = "fsl,etsec-ptp"; 737 reg = <0x0 0x2d10e00 0x0 0xb0>; 738 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 739 fsl,tclk-period = <5>; 740 fsl,tmr-prsc = <2>; 741 fsl,tmr-add = <0xaaaaaaab>; 742 fsl,tmr-fiper1 = <999999995>; 743 fsl,tmr-fiper2 = <999999995>; 744 fsl,max-adj = <499999999>; 745 fsl,extts-fifo; 746 }; 747 748 enet0: ethernet@2d10000 { 749 compatible = "fsl,etsec2"; 750 device_type = "network"; 751 #address-cells = <2>; 752 #size-cells = <2>; 753 interrupt-parent = <&gic>; 754 model = "eTSEC"; 755 fsl,magic-packet; 756 ranges; 757 dma-coherent; 758 759 queue-group@2d10000 { 760 #address-cells = <2>; 761 #size-cells = <2>; 762 reg = <0x0 0x2d10000 0x0 0x1000>; 763 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 766 }; 767 768 queue-group@2d14000 { 769 #address-cells = <2>; 770 #size-cells = <2>; 771 reg = <0x0 0x2d14000 0x0 0x1000>; 772 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 775 }; 776 }; 777 778 enet1: ethernet@2d50000 { 779 compatible = "fsl,etsec2"; 780 device_type = "network"; 781 #address-cells = <2>; 782 #size-cells = <2>; 783 interrupt-parent = <&gic>; 784 model = "eTSEC"; 785 ranges; 786 dma-coherent; 787 788 queue-group@2d50000 { 789 #address-cells = <2>; 790 #size-cells = <2>; 791 reg = <0x0 0x2d50000 0x0 0x1000>; 792 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 795 }; 796 797 queue-group@2d54000 { 798 #address-cells = <2>; 799 #size-cells = <2>; 800 reg = <0x0 0x2d54000 0x0 0x1000>; 801 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 804 }; 805 }; 806 807 enet2: ethernet@2d90000 { 808 compatible = "fsl,etsec2"; 809 device_type = "network"; 810 #address-cells = <2>; 811 #size-cells = <2>; 812 interrupt-parent = <&gic>; 813 model = "eTSEC"; 814 ranges; 815 dma-coherent; 816 817 queue-group@2d90000 { 818 #address-cells = <2>; 819 #size-cells = <2>; 820 reg = <0x0 0x2d90000 0x0 0x1000>; 821 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 824 }; 825 826 queue-group@2d94000 { 827 #address-cells = <2>; 828 #size-cells = <2>; 829 reg = <0x0 0x2d94000 0x0 0x1000>; 830 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 833 }; 834 }; 835 836 usb2: usb@8600000 { 837 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 838 reg = <0x0 0x8600000 0x0 0x1000>; 839 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 840 dr_mode = "host"; 841 phy_type = "ulpi"; 842 }; 843 844 usb3: usb3@3100000 { 845 compatible = "snps,dwc3"; 846 reg = <0x0 0x3100000 0x0 0x10000>; 847 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 848 dr_mode = "host"; 849 snps,quirk-frame-length-adjustment = <0x20>; 850 snps,dis_rxdet_inp3_quirk; 851 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 852 }; 853 854 pcie@3400000 { 855 compatible = "fsl,ls1021a-pcie"; 856 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 857 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 858 reg-names = "regs", "config"; 859 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 860 fsl,pcie-scfg = <&scfg 0>; 861 #address-cells = <3>; 862 #size-cells = <2>; 863 device_type = "pci"; 864 num-viewport = <6>; 865 bus-range = <0x0 0xff>; 866 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 867 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 868 msi-parent = <&msi1>, <&msi2>; 869 #interrupt-cells = <1>; 870 interrupt-map-mask = <0 0 0 7>; 871 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 872 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 873 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 874 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 875 status = "disabled"; 876 }; 877 878 pcie@3500000 { 879 compatible = "fsl,ls1021a-pcie"; 880 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ 881 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 882 reg-names = "regs", "config"; 883 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 884 fsl,pcie-scfg = <&scfg 1>; 885 #address-cells = <3>; 886 #size-cells = <2>; 887 device_type = "pci"; 888 num-viewport = <6>; 889 bus-range = <0x0 0xff>; 890 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 891 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 892 msi-parent = <&msi1>, <&msi2>; 893 #interrupt-cells = <1>; 894 interrupt-map-mask = <0 0 0 7>; 895 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 896 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 897 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 898 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 899 status = "disabled"; 900 }; 901 902 can0: can@2a70000 { 903 compatible = "fsl,ls1021ar2-flexcan"; 904 reg = <0x0 0x2a70000 0x0 0x1000>; 905 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 907 clock-names = "ipg", "per"; 908 big-endian; 909 }; 910 911 can1: can@2a80000 { 912 compatible = "fsl,ls1021ar2-flexcan"; 913 reg = <0x0 0x2a80000 0x0 0x1000>; 914 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 916 clock-names = "ipg", "per"; 917 big-endian; 918 }; 919 920 can2: can@2a90000 { 921 compatible = "fsl,ls1021ar2-flexcan"; 922 reg = <0x0 0x2a90000 0x0 0x1000>; 923 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 925 clock-names = "ipg", "per"; 926 big-endian; 927 }; 928 929 can3: can@2aa0000 { 930 compatible = "fsl,ls1021ar2-flexcan"; 931 reg = <0x0 0x2aa0000 0x0 0x1000>; 932 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 934 clock-names = "ipg", "per"; 935 big-endian; 936 }; 937 938 ocram1: sram@10000000 { 939 compatible = "mmio-sram"; 940 reg = <0x0 0x10000000 0x0 0x10000>; 941 #address-cells = <1>; 942 #size-cells = <1>; 943 ranges = <0x0 0x0 0x10000000 0x10000>; 944 }; 945 946 ocram2: sram@10010000 { 947 compatible = "mmio-sram"; 948 reg = <0x0 0x10010000 0x0 0x10000>; 949 #address-cells = <1>; 950 #size-cells = <1>; 951 ranges = <0x0 0x0 0x10010000 0x10000>; 952 }; 953 954 qdma: dma-controller@8390000 { 955 compatible = "fsl,ls1021a-qdma"; 956 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 957 <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 958 <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 959 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 962 interrupt-names = "qdma-error", 963 "qdma-queue0", "qdma-queue1"; 964 dma-channels = <8>; 965 block-number = <1>; 966 block-offset = <0x1000>; 967 fsl,dma-queues = <2>; 968 status-sizes = <64>; 969 queue-sizes = <64 64>; 970 big-endian; 971 }; 972 973 rcpm: power-controller@1ee2140 { 974 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; 975 reg = <0x0 0x1ee2140 0x0 0x8>; 976 #fsl,rcpm-wakeup-cells = <2>; 977 }; 978 979 ftm_alarm0: timer0@29d0000 { 980 compatible = "fsl,ls1021a-ftm-alarm"; 981 reg = <0x0 0x29d0000 0x0 0x10000>; 982 reg-names = "ftm"; 983 fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>; 984 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 985 big-endian; 986 }; 987 }; 988 989 thermal-zones { 990 cpu_thermal: cpu-thermal { 991 polling-delay-passive = <1000>; 992 polling-delay = <5000>; 993 994 thermal-sensors = <&tmu 0>; 995 996 trips { 997 cpu_alert: cpu-alert { 998 temperature = <85000>; 999 hysteresis = <2000>; 1000 type = "passive"; 1001 }; 1002 cpu_crit: cpu-crit { 1003 temperature = <95000>; 1004 hysteresis = <2000>; 1005 type = "critical"; 1006 }; 1007 }; 1008 1009 cooling-maps { 1010 map0 { 1011 trip = <&cpu_alert>; 1012 cooling-device = 1013 <&cpu0 THERMAL_NO_LIMIT 1014 THERMAL_NO_LIMIT>, 1015 <&cpu1 THERMAL_NO_LIMIT 1016 THERMAL_NO_LIMIT>; 1017 }; 1018 }; 1019 }; 1020 }; 1021}; 1022