1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2013 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/interrupt-controller/irq.h> 6#include "imx6sl-pinfunc.h" 7#include <dt-bindings/clock/imx6sl-clock.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 /* 13 * The decompressor and also some bootloaders rely on a 14 * pre-existing /chosen node to be available to insert the 15 * command line and merge other ATAGS info. 16 */ 17 chosen {}; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 mmc0 = &usdhc1; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc3; 32 mmc3 = &usdhc4; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 serial4 = &uart5; 38 spi0 = &ecspi1; 39 spi1 = &ecspi2; 40 spi2 = &ecspi3; 41 spi3 = &ecspi4; 42 usb0 = &usbotg1; 43 usb1 = &usbotg2; 44 usb2 = &usbh; 45 usbphy0 = &usbphy1; 46 usbphy1 = &usbphy2; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu@0 { 54 compatible = "arm,cortex-a9"; 55 device_type = "cpu"; 56 reg = <0x0>; 57 next-level-cache = <&L2>; 58 operating-points = < 59 /* kHz uV */ 60 996000 1275000 61 792000 1175000 62 396000 975000 63 >; 64 fsl,soc-operating-points = < 65 /* ARM kHz SOC-PU uV */ 66 996000 1225000 67 792000 1175000 68 396000 1175000 69 >; 70 clock-latency = <61036>; /* two CLK32 periods */ 71 #cooling-cells = <2>; 72 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, 73 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, 74 <&clks IMX6SL_CLK_PLL1_SYS>; 75 clock-names = "arm", "pll2_pfd2_396m", "step", 76 "pll1_sw", "pll1_sys"; 77 arm-supply = <®_arm>; 78 pu-supply = <®_pu>; 79 soc-supply = <®_soc>; 80 nvmem-cells = <&cpu_speed_grade>; 81 nvmem-cell-names = "speed_grade"; 82 }; 83 }; 84 85 clocks { 86 ckil { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <32768>; 90 }; 91 92 osc { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <24000000>; 96 }; 97 }; 98 99 pmu { 100 compatible = "arm,cortex-a9-pmu"; 101 interrupt-parent = <&gpc>; 102 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 103 }; 104 105 usbphynop1: usbphynop1 { 106 compatible = "usb-nop-xceiv"; 107 #phy-cells = <0>; 108 }; 109 110 soc { 111 #address-cells = <1>; 112 #size-cells = <1>; 113 compatible = "simple-bus"; 114 interrupt-parent = <&gpc>; 115 ranges; 116 117 ocram: sram@900000 { 118 compatible = "mmio-sram"; 119 reg = <0x00900000 0x20000>; 120 ranges = <0 0x00900000 0x20000>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 clocks = <&clks IMX6SL_CLK_OCRAM>; 124 }; 125 126 intc: interrupt-controller@a01000 { 127 compatible = "arm,cortex-a9-gic"; 128 #interrupt-cells = <3>; 129 interrupt-controller; 130 reg = <0x00a01000 0x1000>, 131 <0x00a00100 0x100>; 132 interrupt-parent = <&intc>; 133 }; 134 135 L2: cache-controller@a02000 { 136 compatible = "arm,pl310-cache"; 137 reg = <0x00a02000 0x1000>; 138 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 139 cache-unified; 140 cache-level = <2>; 141 arm,tag-latency = <4 2 3>; 142 arm,data-latency = <4 2 3>; 143 }; 144 145 aips1: bus@2000000 { 146 compatible = "fsl,aips-bus", "simple-bus"; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 reg = <0x02000000 0x100000>; 150 ranges; 151 152 spba: spba-bus@2000000 { 153 compatible = "fsl,spba-bus", "simple-bus"; 154 #address-cells = <1>; 155 #size-cells = <1>; 156 reg = <0x02000000 0x40000>; 157 ranges; 158 159 spdif: spdif@2004000 { 160 compatible = "fsl,imx6sl-spdif", 161 "fsl,imx35-spdif"; 162 reg = <0x02004000 0x4000>; 163 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 164 dmas = <&sdma 14 18 0>, 165 <&sdma 15 18 0>; 166 dma-names = "rx", "tx"; 167 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, 168 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, 169 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, 170 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, 171 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; 172 clock-names = "core", "rxtx0", 173 "rxtx1", "rxtx2", 174 "rxtx3", "rxtx4", 175 "rxtx5", "rxtx6", 176 "rxtx7", "spba"; 177 status = "disabled"; 178 }; 179 180 ecspi1: spi@2008000 { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 184 reg = <0x02008000 0x4000>; 185 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&clks IMX6SL_CLK_ECSPI1>, 187 <&clks IMX6SL_CLK_ECSPI1>; 188 clock-names = "ipg", "per"; 189 status = "disabled"; 190 }; 191 192 ecspi2: spi@200c000 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 196 reg = <0x0200c000 0x4000>; 197 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clks IMX6SL_CLK_ECSPI2>, 199 <&clks IMX6SL_CLK_ECSPI2>; 200 clock-names = "ipg", "per"; 201 status = "disabled"; 202 }; 203 204 ecspi3: spi@2010000 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 208 reg = <0x02010000 0x4000>; 209 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&clks IMX6SL_CLK_ECSPI3>, 211 <&clks IMX6SL_CLK_ECSPI3>; 212 clock-names = "ipg", "per"; 213 status = "disabled"; 214 }; 215 216 ecspi4: spi@2014000 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 220 reg = <0x02014000 0x4000>; 221 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&clks IMX6SL_CLK_ECSPI4>, 223 <&clks IMX6SL_CLK_ECSPI4>; 224 clock-names = "ipg", "per"; 225 status = "disabled"; 226 }; 227 228 uart5: serial@2018000 { 229 compatible = "fsl,imx6sl-uart", 230 "fsl,imx6q-uart", "fsl,imx21-uart"; 231 reg = <0x02018000 0x4000>; 232 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&clks IMX6SL_CLK_UART>, 234 <&clks IMX6SL_CLK_UART_SERIAL>; 235 clock-names = "ipg", "per"; 236 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 237 dma-names = "rx", "tx"; 238 status = "disabled"; 239 }; 240 241 uart1: serial@2020000 { 242 compatible = "fsl,imx6sl-uart", 243 "fsl,imx6q-uart", "fsl,imx21-uart"; 244 reg = <0x02020000 0x4000>; 245 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&clks IMX6SL_CLK_UART>, 247 <&clks IMX6SL_CLK_UART_SERIAL>; 248 clock-names = "ipg", "per"; 249 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 250 dma-names = "rx", "tx"; 251 status = "disabled"; 252 }; 253 254 uart2: serial@2024000 { 255 compatible = "fsl,imx6sl-uart", 256 "fsl,imx6q-uart", "fsl,imx21-uart"; 257 reg = <0x02024000 0x4000>; 258 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&clks IMX6SL_CLK_UART>, 260 <&clks IMX6SL_CLK_UART_SERIAL>; 261 clock-names = "ipg", "per"; 262 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 263 dma-names = "rx", "tx"; 264 status = "disabled"; 265 }; 266 267 ssi1: ssi@2028000 { 268 #sound-dai-cells = <0>; 269 compatible = "fsl,imx6sl-ssi", 270 "fsl,imx51-ssi"; 271 reg = <0x02028000 0x4000>; 272 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clks IMX6SL_CLK_SSI1_IPG>, 274 <&clks IMX6SL_CLK_SSI1>; 275 clock-names = "ipg", "baud"; 276 dmas = <&sdma 37 1 0>, 277 <&sdma 38 1 0>; 278 dma-names = "rx", "tx"; 279 fsl,fifo-depth = <15>; 280 status = "disabled"; 281 }; 282 283 ssi2: ssi@202c000 { 284 #sound-dai-cells = <0>; 285 compatible = "fsl,imx6sl-ssi", 286 "fsl,imx51-ssi"; 287 reg = <0x0202c000 0x4000>; 288 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&clks IMX6SL_CLK_SSI2_IPG>, 290 <&clks IMX6SL_CLK_SSI2>; 291 clock-names = "ipg", "baud"; 292 dmas = <&sdma 41 1 0>, 293 <&sdma 42 1 0>; 294 dma-names = "rx", "tx"; 295 fsl,fifo-depth = <15>; 296 status = "disabled"; 297 }; 298 299 ssi3: ssi@2030000 { 300 #sound-dai-cells = <0>; 301 compatible = "fsl,imx6sl-ssi", 302 "fsl,imx51-ssi"; 303 reg = <0x02030000 0x4000>; 304 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clks IMX6SL_CLK_SSI3_IPG>, 306 <&clks IMX6SL_CLK_SSI3>; 307 clock-names = "ipg", "baud"; 308 dmas = <&sdma 45 1 0>, 309 <&sdma 46 1 0>; 310 dma-names = "rx", "tx"; 311 fsl,fifo-depth = <15>; 312 status = "disabled"; 313 }; 314 315 uart3: serial@2034000 { 316 compatible = "fsl,imx6sl-uart", 317 "fsl,imx6q-uart", "fsl,imx21-uart"; 318 reg = <0x02034000 0x4000>; 319 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&clks IMX6SL_CLK_UART>, 321 <&clks IMX6SL_CLK_UART_SERIAL>; 322 clock-names = "ipg", "per"; 323 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 324 dma-names = "rx", "tx"; 325 status = "disabled"; 326 }; 327 328 uart4: serial@2038000 { 329 compatible = "fsl,imx6sl-uart", 330 "fsl,imx6q-uart", "fsl,imx21-uart"; 331 reg = <0x02038000 0x4000>; 332 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&clks IMX6SL_CLK_UART>, 334 <&clks IMX6SL_CLK_UART_SERIAL>; 335 clock-names = "ipg", "per"; 336 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 }; 341 342 pwm1: pwm@2080000 { 343 #pwm-cells = <3>; 344 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 345 reg = <0x02080000 0x4000>; 346 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&clks IMX6SL_CLK_PERCLK>, 348 <&clks IMX6SL_CLK_PWM1>; 349 clock-names = "ipg", "per"; 350 }; 351 352 pwm2: pwm@2084000 { 353 #pwm-cells = <3>; 354 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 355 reg = <0x02084000 0x4000>; 356 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&clks IMX6SL_CLK_PERCLK>, 358 <&clks IMX6SL_CLK_PWM2>; 359 clock-names = "ipg", "per"; 360 }; 361 362 pwm3: pwm@2088000 { 363 #pwm-cells = <3>; 364 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 365 reg = <0x02088000 0x4000>; 366 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&clks IMX6SL_CLK_PERCLK>, 368 <&clks IMX6SL_CLK_PWM3>; 369 clock-names = "ipg", "per"; 370 }; 371 372 pwm4: pwm@208c000 { 373 #pwm-cells = <3>; 374 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 375 reg = <0x0208c000 0x4000>; 376 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clks IMX6SL_CLK_PERCLK>, 378 <&clks IMX6SL_CLK_PWM4>; 379 clock-names = "ipg", "per"; 380 }; 381 382 gpt: timer@2098000 { 383 compatible = "fsl,imx6sl-gpt"; 384 reg = <0x02098000 0x4000>; 385 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clks IMX6SL_CLK_GPT>, 387 <&clks IMX6SL_CLK_GPT_SERIAL>; 388 clock-names = "ipg", "per"; 389 }; 390 391 gpio1: gpio@209c000 { 392 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 393 reg = <0x0209c000 0x4000>; 394 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 395 <0 67 IRQ_TYPE_LEVEL_HIGH>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, 401 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, 402 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, 403 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, 404 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, 405 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; 406 }; 407 408 gpio2: gpio@20a0000 { 409 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 410 reg = <0x020a0000 0x4000>; 411 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 412 <0 69 IRQ_TYPE_LEVEL_HIGH>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, 418 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, 419 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, 420 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, 421 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, 422 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, 423 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; 424 }; 425 426 gpio3: gpio@20a4000 { 427 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 428 reg = <0x020a4000 0x4000>; 429 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 430 <0 71 IRQ_TYPE_LEVEL_HIGH>; 431 gpio-controller; 432 #gpio-cells = <2>; 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, 436 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, 437 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, 438 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, 439 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, 440 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, 441 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, 442 <&iomuxc 31 102 1>; 443 }; 444 445 gpio4: gpio@20a8000 { 446 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 447 reg = <0x020a8000 0x4000>; 448 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 449 <0 73 IRQ_TYPE_LEVEL_HIGH>; 450 gpio-controller; 451 #gpio-cells = <2>; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, 455 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, 456 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, 457 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, 458 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, 459 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, 460 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, 461 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, 462 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, 463 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, 464 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, 465 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, 466 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, 467 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, 468 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; 469 }; 470 471 gpio5: gpio@20ac000 { 472 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 473 reg = <0x020ac000 0x4000>; 474 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 475 <0 75 IRQ_TYPE_LEVEL_HIGH>; 476 gpio-controller; 477 #gpio-cells = <2>; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, 481 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, 482 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, 483 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, 484 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, 485 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, 486 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, 487 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, 488 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, 489 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, 490 <&iomuxc 21 161 1>; 491 }; 492 493 kpp: keypad@20b8000 { 494 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; 495 reg = <0x020b8000 0x4000>; 496 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&clks IMX6SL_CLK_IPG>; 498 status = "disabled"; 499 }; 500 501 wdog1: watchdog@20bc000 { 502 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 503 reg = <0x020bc000 0x4000>; 504 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clks IMX6SL_CLK_IPG>; 506 }; 507 508 wdog2: watchdog@20c0000 { 509 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 510 reg = <0x020c0000 0x4000>; 511 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clks IMX6SL_CLK_IPG>; 513 status = "disabled"; 514 }; 515 516 clks: clock-controller@20c4000 { 517 compatible = "fsl,imx6sl-ccm"; 518 reg = <0x020c4000 0x4000>; 519 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 520 <0 88 IRQ_TYPE_LEVEL_HIGH>; 521 #clock-cells = <1>; 522 }; 523 524 anatop: anatop@20c8000 { 525 compatible = "fsl,imx6sl-anatop", 526 "fsl,imx6q-anatop", 527 "syscon", "simple-mfd"; 528 reg = <0x020c8000 0x1000>; 529 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 530 <0 54 IRQ_TYPE_LEVEL_HIGH>, 531 <0 127 IRQ_TYPE_LEVEL_HIGH>; 532 533 reg_vdd1p1: regulator-1p1 { 534 compatible = "fsl,anatop-regulator"; 535 regulator-name = "vdd1p1"; 536 regulator-min-microvolt = <1000000>; 537 regulator-max-microvolt = <1200000>; 538 regulator-always-on; 539 anatop-reg-offset = <0x110>; 540 anatop-vol-bit-shift = <8>; 541 anatop-vol-bit-width = <5>; 542 anatop-min-bit-val = <4>; 543 anatop-min-voltage = <800000>; 544 anatop-max-voltage = <1375000>; 545 anatop-enable-bit = <0>; 546 }; 547 548 reg_vdd3p0: regulator-3p0 { 549 compatible = "fsl,anatop-regulator"; 550 regulator-name = "vdd3p0"; 551 regulator-min-microvolt = <2800000>; 552 regulator-max-microvolt = <3150000>; 553 regulator-always-on; 554 anatop-reg-offset = <0x120>; 555 anatop-vol-bit-shift = <8>; 556 anatop-vol-bit-width = <5>; 557 anatop-min-bit-val = <0>; 558 anatop-min-voltage = <2625000>; 559 anatop-max-voltage = <3400000>; 560 anatop-enable-bit = <0>; 561 }; 562 563 reg_vdd2p5: regulator-2p5 { 564 compatible = "fsl,anatop-regulator"; 565 regulator-name = "vdd2p5"; 566 regulator-min-microvolt = <2250000>; 567 regulator-max-microvolt = <2750000>; 568 regulator-always-on; 569 anatop-reg-offset = <0x130>; 570 anatop-vol-bit-shift = <8>; 571 anatop-vol-bit-width = <5>; 572 anatop-min-bit-val = <0>; 573 anatop-min-voltage = <2100000>; 574 anatop-max-voltage = <2850000>; 575 anatop-enable-bit = <0>; 576 }; 577 578 reg_arm: regulator-vddcore { 579 compatible = "fsl,anatop-regulator"; 580 regulator-name = "vddarm"; 581 regulator-min-microvolt = <725000>; 582 regulator-max-microvolt = <1450000>; 583 regulator-always-on; 584 anatop-reg-offset = <0x140>; 585 anatop-vol-bit-shift = <0>; 586 anatop-vol-bit-width = <5>; 587 anatop-delay-reg-offset = <0x170>; 588 anatop-delay-bit-shift = <24>; 589 anatop-delay-bit-width = <2>; 590 anatop-min-bit-val = <1>; 591 anatop-min-voltage = <725000>; 592 anatop-max-voltage = <1450000>; 593 }; 594 595 reg_pu: regulator-vddpu { 596 compatible = "fsl,anatop-regulator"; 597 regulator-name = "vddpu"; 598 regulator-min-microvolt = <725000>; 599 regulator-max-microvolt = <1450000>; 600 anatop-reg-offset = <0x140>; 601 anatop-vol-bit-shift = <9>; 602 anatop-vol-bit-width = <5>; 603 anatop-delay-reg-offset = <0x170>; 604 anatop-delay-bit-shift = <26>; 605 anatop-delay-bit-width = <2>; 606 anatop-min-bit-val = <1>; 607 anatop-min-voltage = <725000>; 608 anatop-max-voltage = <1450000>; 609 }; 610 611 reg_soc: regulator-vddsoc { 612 compatible = "fsl,anatop-regulator"; 613 regulator-name = "vddsoc"; 614 regulator-min-microvolt = <725000>; 615 regulator-max-microvolt = <1450000>; 616 regulator-always-on; 617 anatop-reg-offset = <0x140>; 618 anatop-vol-bit-shift = <18>; 619 anatop-vol-bit-width = <5>; 620 anatop-delay-reg-offset = <0x170>; 621 anatop-delay-bit-shift = <28>; 622 anatop-delay-bit-width = <2>; 623 anatop-min-bit-val = <1>; 624 anatop-min-voltage = <725000>; 625 anatop-max-voltage = <1450000>; 626 }; 627 628 tempmon: tempmon { 629 compatible = "fsl,imx6q-tempmon"; 630 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-parent = <&gpc>; 632 fsl,tempmon = <&anatop>; 633 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 634 nvmem-cell-names = "calib", "temp_grade"; 635 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; 636 }; 637 }; 638 639 usbphy1: usbphy@20c9000 { 640 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 641 reg = <0x020c9000 0x1000>; 642 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&clks IMX6SL_CLK_USBPHY1>; 644 fsl,anatop = <&anatop>; 645 }; 646 647 usbphy2: usbphy@20ca000 { 648 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 649 reg = <0x020ca000 0x1000>; 650 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&clks IMX6SL_CLK_USBPHY2>; 652 fsl,anatop = <&anatop>; 653 }; 654 655 snvs: snvs@20cc000 { 656 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 657 reg = <0x020cc000 0x4000>; 658 659 snvs_rtc: snvs-rtc-lp { 660 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 661 regmap = <&snvs>; 662 offset = <0x34>; 663 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 664 <0 20 IRQ_TYPE_LEVEL_HIGH>; 665 }; 666 667 snvs_poweroff: snvs-poweroff { 668 compatible = "syscon-poweroff"; 669 regmap = <&snvs>; 670 offset = <0x38>; 671 value = <0x60>; 672 mask = <0x60>; 673 status = "disabled"; 674 }; 675 }; 676 677 epit1: epit@20d0000 { 678 reg = <0x020d0000 0x4000>; 679 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 680 }; 681 682 epit2: epit@20d4000 { 683 reg = <0x020d4000 0x4000>; 684 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 685 }; 686 687 src: reset-controller@20d8000 { 688 compatible = "fsl,imx6sl-src", "fsl,imx51-src"; 689 reg = <0x020d8000 0x4000>; 690 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 691 <0 96 IRQ_TYPE_LEVEL_HIGH>; 692 #reset-cells = <1>; 693 }; 694 695 gpc: gpc@20dc000 { 696 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; 697 reg = <0x020dc000 0x4000>; 698 interrupt-controller; 699 #interrupt-cells = <3>; 700 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-parent = <&intc>; 702 clocks = <&clks IMX6SL_CLK_IPG>; 703 clock-names = "ipg"; 704 705 pgc { 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 power-domain@0 { 710 reg = <0>; 711 #power-domain-cells = <0>; 712 }; 713 714 pd_pu: power-domain@1 { 715 reg = <1>; 716 #power-domain-cells = <0>; 717 power-supply = <®_pu>; 718 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, 719 <&clks IMX6SL_CLK_GPU2D_PODF>; 720 }; 721 722 pd_disp: power-domain@2 { 723 reg = <2>; 724 #power-domain-cells = <0>; 725 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, 726 <&clks IMX6SL_CLK_LCDIF_PIX>, 727 <&clks IMX6SL_CLK_EPDC_AXI>, 728 <&clks IMX6SL_CLK_EPDC_PIX>, 729 <&clks IMX6SL_CLK_PXP_AXI>; 730 }; 731 }; 732 }; 733 734 gpr: iomuxc-gpr@20e0000 { 735 compatible = "fsl,imx6sl-iomuxc-gpr", 736 "fsl,imx6q-iomuxc-gpr", "syscon"; 737 reg = <0x020e0000 0x38>; 738 }; 739 740 iomuxc: pinctrl@20e0000 { 741 compatible = "fsl,imx6sl-iomuxc"; 742 reg = <0x020e0000 0x4000>; 743 }; 744 745 csi: csi@20e4000 { 746 reg = <0x020e4000 0x4000>; 747 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 748 }; 749 750 spdc: spdc@20e8000 { 751 reg = <0x020e8000 0x4000>; 752 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 753 }; 754 755 sdma: dma-controller@20ec000 { 756 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; 757 reg = <0x020ec000 0x4000>; 758 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&clks IMX6SL_CLK_SDMA>, 760 <&clks IMX6SL_CLK_AHB>; 761 clock-names = "ipg", "ahb"; 762 #dma-cells = <3>; 763 /* imx6sl reuses imx6q sdma firmware */ 764 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 765 }; 766 767 pxp: pxp@20f0000 { 768 reg = <0x020f0000 0x4000>; 769 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 770 }; 771 772 epdc: epdc@20f4000 { 773 reg = <0x020f4000 0x4000>; 774 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 775 }; 776 777 lcdif: lcdif@20f8000 { 778 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; 779 reg = <0x020f8000 0x4000>; 780 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, 782 <&clks IMX6SL_CLK_LCDIF_AXI>, 783 <&clks IMX6SL_CLK_DUMMY>; 784 clock-names = "pix", "axi", "disp_axi"; 785 status = "disabled"; 786 power-domains = <&pd_disp>; 787 }; 788 789 dcp: crypto@20fc000 { 790 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; 791 reg = <0x020fc000 0x4000>; 792 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, 793 <0 100 IRQ_TYPE_LEVEL_HIGH>, 794 <0 101 IRQ_TYPE_LEVEL_HIGH>; 795 }; 796 }; 797 798 aips2: bus@2100000 { 799 compatible = "fsl,aips-bus", "simple-bus"; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 reg = <0x02100000 0x100000>; 803 ranges; 804 805 usbotg1: usb@2184000 { 806 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 807 reg = <0x02184000 0x200>; 808 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&clks IMX6SL_CLK_USBOH3>; 810 fsl,usbphy = <&usbphy1>; 811 fsl,usbmisc = <&usbmisc 0>; 812 ahb-burst-config = <0x0>; 813 tx-burst-size-dword = <0x10>; 814 rx-burst-size-dword = <0x10>; 815 status = "disabled"; 816 }; 817 818 usbotg2: usb@2184200 { 819 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 820 reg = <0x02184200 0x200>; 821 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&clks IMX6SL_CLK_USBOH3>; 823 fsl,usbphy = <&usbphy2>; 824 fsl,usbmisc = <&usbmisc 1>; 825 ahb-burst-config = <0x0>; 826 tx-burst-size-dword = <0x10>; 827 rx-burst-size-dword = <0x10>; 828 status = "disabled"; 829 }; 830 831 usbh: usb@2184400 { 832 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 833 reg = <0x02184400 0x200>; 834 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&clks IMX6SL_CLK_USBOH3>; 836 fsl,usbphy = <&usbphynop1>; 837 phy_type = "hsic"; 838 fsl,usbmisc = <&usbmisc 2>; 839 dr_mode = "host"; 840 ahb-burst-config = <0x0>; 841 tx-burst-size-dword = <0x10>; 842 rx-burst-size-dword = <0x10>; 843 status = "disabled"; 844 }; 845 846 usbmisc: usbmisc@2184800 { 847 #index-cells = <1>; 848 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; 849 reg = <0x02184800 0x200>; 850 clocks = <&clks IMX6SL_CLK_USBOH3>; 851 }; 852 853 fec: ethernet@2188000 { 854 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; 855 reg = <0x02188000 0x4000>; 856 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&clks IMX6SL_CLK_ENET>, 858 <&clks IMX6SL_CLK_ENET_REF>; 859 clock-names = "ipg", "ahb"; 860 status = "disabled"; 861 }; 862 863 usdhc1: mmc@2190000 { 864 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 865 reg = <0x02190000 0x4000>; 866 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&clks IMX6SL_CLK_USDHC1>, 868 <&clks IMX6SL_CLK_USDHC1>, 869 <&clks IMX6SL_CLK_USDHC1>; 870 clock-names = "ipg", "ahb", "per"; 871 bus-width = <4>; 872 status = "disabled"; 873 }; 874 875 usdhc2: mmc@2194000 { 876 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 877 reg = <0x02194000 0x4000>; 878 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clks IMX6SL_CLK_USDHC2>, 880 <&clks IMX6SL_CLK_USDHC2>, 881 <&clks IMX6SL_CLK_USDHC2>; 882 clock-names = "ipg", "ahb", "per"; 883 bus-width = <4>; 884 status = "disabled"; 885 }; 886 887 usdhc3: mmc@2198000 { 888 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 889 reg = <0x02198000 0x4000>; 890 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&clks IMX6SL_CLK_USDHC3>, 892 <&clks IMX6SL_CLK_USDHC3>, 893 <&clks IMX6SL_CLK_USDHC3>; 894 clock-names = "ipg", "ahb", "per"; 895 bus-width = <4>; 896 status = "disabled"; 897 }; 898 899 usdhc4: mmc@219c000 { 900 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 901 reg = <0x0219c000 0x4000>; 902 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&clks IMX6SL_CLK_USDHC4>, 904 <&clks IMX6SL_CLK_USDHC4>, 905 <&clks IMX6SL_CLK_USDHC4>; 906 clock-names = "ipg", "ahb", "per"; 907 bus-width = <4>; 908 status = "disabled"; 909 }; 910 911 i2c1: i2c@21a0000 { 912 #address-cells = <1>; 913 #size-cells = <0>; 914 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 915 reg = <0x021a0000 0x4000>; 916 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&clks IMX6SL_CLK_I2C1>; 918 status = "disabled"; 919 }; 920 921 i2c2: i2c@21a4000 { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 925 reg = <0x021a4000 0x4000>; 926 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&clks IMX6SL_CLK_I2C2>; 928 status = "disabled"; 929 }; 930 931 i2c3: i2c@21a8000 { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 935 reg = <0x021a8000 0x4000>; 936 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&clks IMX6SL_CLK_I2C3>; 938 status = "disabled"; 939 }; 940 941 memory-controller@21b0000 { 942 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; 943 reg = <0x021b0000 0x4000>; 944 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; 945 }; 946 947 rngb: rngb@21b4000 { 948 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; 949 reg = <0x021b4000 0x4000>; 950 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clks IMX6SL_CLK_DUMMY>; 952 }; 953 954 weim: weim@21b8000 { 955 #address-cells = <2>; 956 #size-cells = <1>; 957 reg = <0x021b8000 0x4000>; 958 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 959 fsl,weim-cs-gpr = <&gpr>; 960 status = "disabled"; 961 }; 962 963 ocotp: efuse@21bc000 { 964 compatible = "fsl,imx6sl-ocotp", "syscon"; 965 reg = <0x021bc000 0x4000>; 966 clocks = <&clks IMX6SL_CLK_OCOTP>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 970 cpu_speed_grade: speed-grade@10 { 971 reg = <0x10 4>; 972 }; 973 974 tempmon_calib: calib@38 { 975 reg = <0x38 4>; 976 }; 977 978 tempmon_temp_grade: temp-grade@20 { 979 reg = <0x20 4>; 980 }; 981 }; 982 983 audmux: audmux@21d8000 { 984 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; 985 reg = <0x021d8000 0x4000>; 986 status = "disabled"; 987 }; 988 }; 989 990 gpu_2d: gpu@2200000 { 991 compatible = "vivante,gc"; 992 reg = <0x02200000 0x4000>; 993 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, 995 <&clks IMX6SL_CLK_GPU2D_OVG>; 996 clock-names = "bus", "core"; 997 power-domains = <&pd_pu>; 998 }; 999 1000 gpu_vg: gpu@2204000 { 1001 compatible = "vivante,gc"; 1002 reg = <0x02204000 0x4000>; 1003 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, 1005 <&clks IMX6SL_CLK_GPU2D_OVG>; 1006 clock-names = "bus", "core"; 1007 power-domains = <&pd_pu>; 1008 }; 1009 }; 1010}; 1011