1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: local_intc@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 clocks = <&clocks BCM2835_CLOCK_V3D>, 117 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 118 <&clocks BCM2835_CLOCK_H264>, 119 <&clocks BCM2835_CLOCK_ISP>; 120 clock-names = "v3d", "peri_image", "h264", "isp"; 121 system-power-controller; 122 }; 123 124 rng@7e104000 { 125 compatible = "brcm,bcm2711-rng200"; 126 reg = <0x7e104000 0x28>; 127 }; 128 129 uart2: serial@7e201400 { 130 compatible = "arm,pl011", "arm,primecell"; 131 reg = <0x7e201400 0x200>; 132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&clocks BCM2835_CLOCK_UART>, 134 <&clocks BCM2835_CLOCK_VPU>; 135 clock-names = "uartclk", "apb_pclk"; 136 arm,primecell-periphid = <0x00241011>; 137 status = "disabled"; 138 }; 139 140 uart3: serial@7e201600 { 141 compatible = "arm,pl011", "arm,primecell"; 142 reg = <0x7e201600 0x200>; 143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&clocks BCM2835_CLOCK_UART>, 145 <&clocks BCM2835_CLOCK_VPU>; 146 clock-names = "uartclk", "apb_pclk"; 147 arm,primecell-periphid = <0x00241011>; 148 status = "disabled"; 149 }; 150 151 uart4: serial@7e201800 { 152 compatible = "arm,pl011", "arm,primecell"; 153 reg = <0x7e201800 0x200>; 154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&clocks BCM2835_CLOCK_UART>, 156 <&clocks BCM2835_CLOCK_VPU>; 157 clock-names = "uartclk", "apb_pclk"; 158 arm,primecell-periphid = <0x00241011>; 159 status = "disabled"; 160 }; 161 162 uart5: serial@7e201a00 { 163 compatible = "arm,pl011", "arm,primecell"; 164 reg = <0x7e201a00 0x200>; 165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&clocks BCM2835_CLOCK_UART>, 167 <&clocks BCM2835_CLOCK_VPU>; 168 clock-names = "uartclk", "apb_pclk"; 169 arm,primecell-periphid = <0x00241011>; 170 status = "disabled"; 171 }; 172 173 spi3: spi@7e204600 { 174 compatible = "brcm,bcm2835-spi"; 175 reg = <0x7e204600 0x0200>; 176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&clocks BCM2835_CLOCK_VPU>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 status = "disabled"; 181 }; 182 183 spi4: spi@7e204800 { 184 compatible = "brcm,bcm2835-spi"; 185 reg = <0x7e204800 0x0200>; 186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&clocks BCM2835_CLOCK_VPU>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 status = "disabled"; 191 }; 192 193 spi5: spi@7e204a00 { 194 compatible = "brcm,bcm2835-spi"; 195 reg = <0x7e204a00 0x0200>; 196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clocks BCM2835_CLOCK_VPU>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 status = "disabled"; 201 }; 202 203 spi6: spi@7e204c00 { 204 compatible = "brcm,bcm2835-spi"; 205 reg = <0x7e204c00 0x0200>; 206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clocks BCM2835_CLOCK_VPU>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 status = "disabled"; 211 }; 212 213 i2c3: i2c@7e205600 { 214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 215 reg = <0x7e205600 0x200>; 216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&clocks BCM2835_CLOCK_VPU>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c4: i2c@7e205800 { 224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 225 reg = <0x7e205800 0x200>; 226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&clocks BCM2835_CLOCK_VPU>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c5: i2c@7e205a00 { 234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 235 reg = <0x7e205a00 0x200>; 236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&clocks BCM2835_CLOCK_VPU>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c6: i2c@7e205c00 { 244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 245 reg = <0x7e205c00 0x200>; 246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clocks BCM2835_CLOCK_VPU>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 pixelvalve0: pixelvalve@7e206000 { 254 compatible = "brcm,bcm2711-pixelvalve0"; 255 reg = <0x7e206000 0x100>; 256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 257 status = "disabled"; 258 }; 259 260 pixelvalve1: pixelvalve@7e207000 { 261 compatible = "brcm,bcm2711-pixelvalve1"; 262 reg = <0x7e207000 0x100>; 263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 264 status = "disabled"; 265 }; 266 267 pixelvalve2: pixelvalve@7e20a000 { 268 compatible = "brcm,bcm2711-pixelvalve2"; 269 reg = <0x7e20a000 0x100>; 270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 271 status = "disabled"; 272 }; 273 274 pwm1: pwm@7e20c800 { 275 compatible = "brcm,bcm2835-pwm"; 276 reg = <0x7e20c800 0x28>; 277 clocks = <&clocks BCM2835_CLOCK_PWM>; 278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clock-rates = <10000000>; 280 #pwm-cells = <2>; 281 status = "disabled"; 282 }; 283 284 pixelvalve4: pixelvalve@7e216000 { 285 compatible = "brcm,bcm2711-pixelvalve4"; 286 reg = <0x7e216000 0x100>; 287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 288 status = "disabled"; 289 }; 290 291 hvs: hvs@7e400000 { 292 compatible = "brcm,bcm2711-hvs"; 293 reg = <0x7e400000 0x8000>; 294 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 295 }; 296 297 pixelvalve3: pixelvalve@7ec12000 { 298 compatible = "brcm,bcm2711-pixelvalve3"; 299 reg = <0x7ec12000 0x100>; 300 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 301 status = "disabled"; 302 }; 303 304 dvp: clock@7ef00000 { 305 compatible = "brcm,brcm2711-dvp"; 306 reg = <0x7ef00000 0x10>; 307 clocks = <&clk_108MHz>; 308 #clock-cells = <1>; 309 #reset-cells = <1>; 310 }; 311 312 hdmi0: hdmi@7ef00700 { 313 compatible = "brcm,bcm2711-hdmi0"; 314 reg = <0x7ef00700 0x300>, 315 <0x7ef00300 0x200>, 316 <0x7ef00f00 0x80>, 317 <0x7ef00f80 0x80>, 318 <0x7ef01b00 0x200>, 319 <0x7ef01f00 0x400>, 320 <0x7ef00200 0x80>, 321 <0x7ef04300 0x100>, 322 <0x7ef20000 0x100>; 323 reg-names = "hdmi", 324 "dvp", 325 "phy", 326 "rm", 327 "packet", 328 "metadata", 329 "csc", 330 "cec", 331 "hd"; 332 clock-names = "hdmi", "bvb", "audio", "cec"; 333 resets = <&dvp 0>; 334 ddc = <&ddc0>; 335 dmas = <&dma 10>; 336 dma-names = "audio-rx"; 337 status = "disabled"; 338 }; 339 340 ddc0: i2c@7ef04500 { 341 compatible = "brcm,bcm2711-hdmi-i2c"; 342 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 343 reg-names = "bsc", "auto-i2c"; 344 clock-frequency = <97500>; 345 status = "disabled"; 346 }; 347 348 hdmi1: hdmi@7ef05700 { 349 compatible = "brcm,bcm2711-hdmi1"; 350 reg = <0x7ef05700 0x300>, 351 <0x7ef05300 0x200>, 352 <0x7ef05f00 0x80>, 353 <0x7ef05f80 0x80>, 354 <0x7ef06b00 0x200>, 355 <0x7ef06f00 0x400>, 356 <0x7ef00280 0x80>, 357 <0x7ef09300 0x100>, 358 <0x7ef20000 0x100>; 359 reg-names = "hdmi", 360 "dvp", 361 "phy", 362 "rm", 363 "packet", 364 "metadata", 365 "csc", 366 "cec", 367 "hd"; 368 ddc = <&ddc1>; 369 clock-names = "hdmi", "bvb", "audio", "cec"; 370 resets = <&dvp 1>; 371 dmas = <&dma 17>; 372 dma-names = "audio-rx"; 373 status = "disabled"; 374 }; 375 376 ddc1: i2c@7ef09500 { 377 compatible = "brcm,bcm2711-hdmi-i2c"; 378 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 379 reg-names = "bsc", "auto-i2c"; 380 clock-frequency = <97500>; 381 status = "disabled"; 382 }; 383 }; 384 385 /* 386 * emmc2 has different DMA constraints based on SoC revisions. It was 387 * moved into its own bus, so as for RPi4's firmware to update them. 388 * The firmware will find whether the emmc2bus alias is defined, and if 389 * so, it'll edit the dma-ranges property below accordingly. 390 */ 391 emmc2bus: emmc2bus { 392 compatible = "simple-bus"; 393 #address-cells = <2>; 394 #size-cells = <1>; 395 396 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 397 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 398 399 emmc2: mmc@7e340000 { 400 compatible = "brcm,bcm2711-emmc2"; 401 reg = <0x0 0x7e340000 0x100>; 402 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 404 status = "disabled"; 405 }; 406 }; 407 408 arm-pmu { 409 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 410 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 415 }; 416 417 timer { 418 compatible = "arm,armv8-timer"; 419 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 420 IRQ_TYPE_LEVEL_LOW)>, 421 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 422 IRQ_TYPE_LEVEL_LOW)>, 423 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 424 IRQ_TYPE_LEVEL_LOW)>, 425 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 426 IRQ_TYPE_LEVEL_LOW)>; 427 /* This only applies to the ARMv7 stub */ 428 arm,cpu-registers-not-fw-configured; 429 }; 430 431 cpus: cpus { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 435 436 /* Source for d/i-cache-line-size and d/i-cache-sets 437 * https://developer.arm.com/documentation/100095/0003 438 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en 439 * Source for d/i-cache-size 440 * https://www.raspberrypi.com/documentation/computers 441 * /processors.html#bcm2711 442 */ 443 cpu0: cpu@0 { 444 device_type = "cpu"; 445 compatible = "arm,cortex-a72"; 446 reg = <0>; 447 enable-method = "spin-table"; 448 cpu-release-addr = <0x0 0x000000d8>; 449 d-cache-size = <0x8000>; 450 d-cache-line-size = <64>; 451 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 452 i-cache-size = <0xc000>; 453 i-cache-line-size = <64>; 454 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 455 next-level-cache = <&l2>; 456 }; 457 458 cpu1: cpu@1 { 459 device_type = "cpu"; 460 compatible = "arm,cortex-a72"; 461 reg = <1>; 462 enable-method = "spin-table"; 463 cpu-release-addr = <0x0 0x000000e0>; 464 d-cache-size = <0x8000>; 465 d-cache-line-size = <64>; 466 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 467 i-cache-size = <0xc000>; 468 i-cache-line-size = <64>; 469 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 470 next-level-cache = <&l2>; 471 }; 472 473 cpu2: cpu@2 { 474 device_type = "cpu"; 475 compatible = "arm,cortex-a72"; 476 reg = <2>; 477 enable-method = "spin-table"; 478 cpu-release-addr = <0x0 0x000000e8>; 479 d-cache-size = <0x8000>; 480 d-cache-line-size = <64>; 481 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 482 i-cache-size = <0xc000>; 483 i-cache-line-size = <64>; 484 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 485 next-level-cache = <&l2>; 486 }; 487 488 cpu3: cpu@3 { 489 device_type = "cpu"; 490 compatible = "arm,cortex-a72"; 491 reg = <3>; 492 enable-method = "spin-table"; 493 cpu-release-addr = <0x0 0x000000f0>; 494 d-cache-size = <0x8000>; 495 d-cache-line-size = <64>; 496 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 497 i-cache-size = <0xc000>; 498 i-cache-line-size = <64>; 499 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 500 next-level-cache = <&l2>; 501 }; 502 503 /* Source for d/i-cache-line-size and d/i-cache-sets 504 * https://developer.arm.com/documentation/100095/0003 505 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en 506 * Source for d/i-cache-size 507 * https://www.raspberrypi.com/documentation/computers 508 * /processors.html#bcm2711 509 */ 510 l2: l2-cache0 { 511 compatible = "cache"; 512 cache-size = <0x100000>; 513 cache-line-size = <64>; 514 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set 515 cache-level = <2>; 516 }; 517 }; 518 519 scb { 520 compatible = "simple-bus"; 521 #address-cells = <2>; 522 #size-cells = <1>; 523 524 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 525 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 526 527 pcie0: pcie@7d500000 { 528 compatible = "brcm,bcm2711-pcie"; 529 reg = <0x0 0x7d500000 0x9310>; 530 device_type = "pci"; 531 #address-cells = <3>; 532 #interrupt-cells = <1>; 533 #size-cells = <2>; 534 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 536 interrupt-names = "pcie", "msi"; 537 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 538 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 539 IRQ_TYPE_LEVEL_HIGH>, 540 <0 0 0 2 &gicv2 GIC_SPI 144 541 IRQ_TYPE_LEVEL_HIGH>, 542 <0 0 0 3 &gicv2 GIC_SPI 145 543 IRQ_TYPE_LEVEL_HIGH>, 544 <0 0 0 4 &gicv2 GIC_SPI 146 545 IRQ_TYPE_LEVEL_HIGH>; 546 msi-controller; 547 msi-parent = <&pcie0>; 548 549 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 550 0x0 0x04000000>; 551 /* 552 * The wrapper around the PCIe block has a bug 553 * preventing it from accessing beyond the first 3GB of 554 * memory. 555 */ 556 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 557 0x0 0xc0000000>; 558 brcm,enable-ssc; 559 }; 560 561 genet: ethernet@7d580000 { 562 compatible = "brcm,bcm2711-genet-v5"; 563 reg = <0x0 0x7d580000 0x10000>; 564 #address-cells = <0x1>; 565 #size-cells = <0x1>; 566 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 568 status = "disabled"; 569 570 genet_mdio: mdio@e14 { 571 compatible = "brcm,genet-mdio-v5"; 572 reg = <0xe14 0x8>; 573 reg-names = "mdio"; 574 #address-cells = <0x1>; 575 #size-cells = <0x0>; 576 }; 577 }; 578 }; 579}; 580 581&clk_osc { 582 clock-frequency = <54000000>; 583}; 584 585&clocks { 586 compatible = "brcm,bcm2711-cprman"; 587}; 588 589&cpu_thermal { 590 coefficients = <(-487) 410040>; 591 thermal-sensors = <&thermal>; 592}; 593 594&dsi0 { 595 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 596}; 597 598&dsi1 { 599 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 600}; 601 602&gpio { 603 compatible = "brcm,bcm2711-gpio"; 604 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 608 609 gpio-ranges = <&gpio 0 0 58>; 610 611 gpclk0_gpio49: gpclk0_gpio49 { 612 pin-gpclk { 613 pins = "gpio49"; 614 function = "alt1"; 615 bias-disable; 616 }; 617 }; 618 gpclk1_gpio50: gpclk1_gpio50 { 619 pin-gpclk { 620 pins = "gpio50"; 621 function = "alt1"; 622 bias-disable; 623 }; 624 }; 625 gpclk2_gpio51: gpclk2_gpio51 { 626 pin-gpclk { 627 pins = "gpio51"; 628 function = "alt1"; 629 bias-disable; 630 }; 631 }; 632 633 i2c0_gpio46: i2c0_gpio46 { 634 pin-sda { 635 function = "alt0"; 636 pins = "gpio46"; 637 bias-pull-up; 638 }; 639 pin-scl { 640 function = "alt0"; 641 pins = "gpio47"; 642 bias-disable; 643 }; 644 }; 645 i2c1_gpio46: i2c1_gpio46 { 646 pin-sda { 647 function = "alt1"; 648 pins = "gpio46"; 649 bias-pull-up; 650 }; 651 pin-scl { 652 function = "alt1"; 653 pins = "gpio47"; 654 bias-disable; 655 }; 656 }; 657 i2c3_gpio2: i2c3_gpio2 { 658 pin-sda { 659 function = "alt5"; 660 pins = "gpio2"; 661 bias-pull-up; 662 }; 663 pin-scl { 664 function = "alt5"; 665 pins = "gpio3"; 666 bias-disable; 667 }; 668 }; 669 i2c3_gpio4: i2c3_gpio4 { 670 pin-sda { 671 function = "alt5"; 672 pins = "gpio4"; 673 bias-pull-up; 674 }; 675 pin-scl { 676 function = "alt5"; 677 pins = "gpio5"; 678 bias-disable; 679 }; 680 }; 681 i2c4_gpio6: i2c4_gpio6 { 682 pin-sda { 683 function = "alt5"; 684 pins = "gpio6"; 685 bias-pull-up; 686 }; 687 pin-scl { 688 function = "alt5"; 689 pins = "gpio7"; 690 bias-disable; 691 }; 692 }; 693 i2c4_gpio8: i2c4_gpio8 { 694 pin-sda { 695 function = "alt5"; 696 pins = "gpio8"; 697 bias-pull-up; 698 }; 699 pin-scl { 700 function = "alt5"; 701 pins = "gpio9"; 702 bias-disable; 703 }; 704 }; 705 i2c5_gpio10: i2c5_gpio10 { 706 pin-sda { 707 function = "alt5"; 708 pins = "gpio10"; 709 bias-pull-up; 710 }; 711 pin-scl { 712 function = "alt5"; 713 pins = "gpio11"; 714 bias-disable; 715 }; 716 }; 717 i2c5_gpio12: i2c5_gpio12 { 718 pin-sda { 719 function = "alt5"; 720 pins = "gpio12"; 721 bias-pull-up; 722 }; 723 pin-scl { 724 function = "alt5"; 725 pins = "gpio13"; 726 bias-disable; 727 }; 728 }; 729 i2c6_gpio0: i2c6_gpio0 { 730 pin-sda { 731 function = "alt5"; 732 pins = "gpio0"; 733 bias-pull-up; 734 }; 735 pin-scl { 736 function = "alt5"; 737 pins = "gpio1"; 738 bias-disable; 739 }; 740 }; 741 i2c6_gpio22: i2c6_gpio22 { 742 pin-sda { 743 function = "alt5"; 744 pins = "gpio22"; 745 bias-pull-up; 746 }; 747 pin-scl { 748 function = "alt5"; 749 pins = "gpio23"; 750 bias-disable; 751 }; 752 }; 753 i2c_slave_gpio8: i2c_slave_gpio8 { 754 pins-i2c-slave { 755 pins = "gpio8", 756 "gpio9", 757 "gpio10", 758 "gpio11"; 759 function = "alt3"; 760 }; 761 }; 762 763 jtag_gpio48: jtag_gpio48 { 764 pins-jtag { 765 pins = "gpio48", 766 "gpio49", 767 "gpio50", 768 "gpio51", 769 "gpio52", 770 "gpio53"; 771 function = "alt4"; 772 }; 773 }; 774 775 mii_gpio28: mii_gpio28 { 776 pins-mii { 777 pins = "gpio28", 778 "gpio29", 779 "gpio30", 780 "gpio31"; 781 function = "alt4"; 782 }; 783 }; 784 mii_gpio36: mii_gpio36 { 785 pins-mii { 786 pins = "gpio36", 787 "gpio37", 788 "gpio38", 789 "gpio39"; 790 function = "alt5"; 791 }; 792 }; 793 794 pcm_gpio50: pcm_gpio50 { 795 pins-pcm { 796 pins = "gpio50", 797 "gpio51", 798 "gpio52", 799 "gpio53"; 800 function = "alt2"; 801 }; 802 }; 803 804 pwm0_0_gpio12: pwm0_0_gpio12 { 805 pin-pwm { 806 pins = "gpio12"; 807 function = "alt0"; 808 bias-disable; 809 }; 810 }; 811 pwm0_0_gpio18: pwm0_0_gpio18 { 812 pin-pwm { 813 pins = "gpio18"; 814 function = "alt5"; 815 bias-disable; 816 }; 817 }; 818 pwm1_0_gpio40: pwm1_0_gpio40 { 819 pin-pwm { 820 pins = "gpio40"; 821 function = "alt0"; 822 bias-disable; 823 }; 824 }; 825 pwm0_1_gpio13: pwm0_1_gpio13 { 826 pin-pwm { 827 pins = "gpio13"; 828 function = "alt0"; 829 bias-disable; 830 }; 831 }; 832 pwm0_1_gpio19: pwm0_1_gpio19 { 833 pin-pwm { 834 pins = "gpio19"; 835 function = "alt5"; 836 bias-disable; 837 }; 838 }; 839 pwm1_1_gpio41: pwm1_1_gpio41 { 840 pin-pwm { 841 pins = "gpio41"; 842 function = "alt0"; 843 bias-disable; 844 }; 845 }; 846 pwm0_1_gpio45: pwm0_1_gpio45 { 847 pin-pwm { 848 pins = "gpio45"; 849 function = "alt0"; 850 bias-disable; 851 }; 852 }; 853 pwm0_0_gpio52: pwm0_0_gpio52 { 854 pin-pwm { 855 pins = "gpio52"; 856 function = "alt1"; 857 bias-disable; 858 }; 859 }; 860 pwm0_1_gpio53: pwm0_1_gpio53 { 861 pin-pwm { 862 pins = "gpio53"; 863 function = "alt1"; 864 bias-disable; 865 }; 866 }; 867 868 rgmii_gpio35: rgmii_gpio35 { 869 pin-start-stop { 870 pins = "gpio35"; 871 function = "alt4"; 872 }; 873 pin-rx-ok { 874 pins = "gpio36"; 875 function = "alt4"; 876 }; 877 }; 878 rgmii_irq_gpio34: rgmii_irq_gpio34 { 879 pin-irq { 880 pins = "gpio34"; 881 function = "alt5"; 882 }; 883 }; 884 rgmii_irq_gpio39: rgmii_irq_gpio39 { 885 pin-irq { 886 pins = "gpio39"; 887 function = "alt4"; 888 }; 889 }; 890 rgmii_mdio_gpio28: rgmii_mdio_gpio28 { 891 pins-mdio { 892 pins = "gpio28", 893 "gpio29"; 894 function = "alt5"; 895 }; 896 }; 897 rgmii_mdio_gpio37: rgmii_mdio_gpio37 { 898 pins-mdio { 899 pins = "gpio37", 900 "gpio38"; 901 function = "alt4"; 902 }; 903 }; 904 905 spi0_gpio46: spi0_gpio46 { 906 pins-spi { 907 pins = "gpio46", 908 "gpio47", 909 "gpio48", 910 "gpio49"; 911 function = "alt2"; 912 }; 913 }; 914 spi2_gpio46: spi2_gpio46 { 915 pins-spi { 916 pins = "gpio46", 917 "gpio47", 918 "gpio48", 919 "gpio49", 920 "gpio50"; 921 function = "alt5"; 922 }; 923 }; 924 spi3_gpio0: spi3_gpio0 { 925 pins-spi { 926 pins = "gpio0", 927 "gpio1", 928 "gpio2", 929 "gpio3"; 930 function = "alt3"; 931 }; 932 }; 933 spi4_gpio4: spi4_gpio4 { 934 pins-spi { 935 pins = "gpio4", 936 "gpio5", 937 "gpio6", 938 "gpio7"; 939 function = "alt3"; 940 }; 941 }; 942 spi5_gpio12: spi5_gpio12 { 943 pins-spi { 944 pins = "gpio12", 945 "gpio13", 946 "gpio14", 947 "gpio15"; 948 function = "alt3"; 949 }; 950 }; 951 spi6_gpio18: spi6_gpio18 { 952 pins-spi { 953 pins = "gpio18", 954 "gpio19", 955 "gpio20", 956 "gpio21"; 957 function = "alt3"; 958 }; 959 }; 960 961 uart2_gpio0: uart2_gpio0 { 962 pin-tx { 963 pins = "gpio0"; 964 function = "alt4"; 965 bias-disable; 966 }; 967 pin-rx { 968 pins = "gpio1"; 969 function = "alt4"; 970 bias-pull-up; 971 }; 972 }; 973 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { 974 pin-cts { 975 pins = "gpio2"; 976 function = "alt4"; 977 bias-pull-up; 978 }; 979 pin-rts { 980 pins = "gpio3"; 981 function = "alt4"; 982 bias-disable; 983 }; 984 }; 985 uart3_gpio4: uart3_gpio4 { 986 pin-tx { 987 pins = "gpio4"; 988 function = "alt4"; 989 bias-disable; 990 }; 991 pin-rx { 992 pins = "gpio5"; 993 function = "alt4"; 994 bias-pull-up; 995 }; 996 }; 997 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { 998 pin-cts { 999 pins = "gpio6"; 1000 function = "alt4"; 1001 bias-pull-up; 1002 }; 1003 pin-rts { 1004 pins = "gpio7"; 1005 function = "alt4"; 1006 bias-disable; 1007 }; 1008 }; 1009 uart4_gpio8: uart4_gpio8 { 1010 pin-tx { 1011 pins = "gpio8"; 1012 function = "alt4"; 1013 bias-disable; 1014 }; 1015 pin-rx { 1016 pins = "gpio9"; 1017 function = "alt4"; 1018 bias-pull-up; 1019 }; 1020 }; 1021 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { 1022 pin-cts { 1023 pins = "gpio10"; 1024 function = "alt4"; 1025 bias-pull-up; 1026 }; 1027 pin-rts { 1028 pins = "gpio11"; 1029 function = "alt4"; 1030 bias-disable; 1031 }; 1032 }; 1033 uart5_gpio12: uart5_gpio12 { 1034 pin-tx { 1035 pins = "gpio12"; 1036 function = "alt4"; 1037 bias-disable; 1038 }; 1039 pin-rx { 1040 pins = "gpio13"; 1041 function = "alt4"; 1042 bias-pull-up; 1043 }; 1044 }; 1045 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { 1046 pin-cts { 1047 pins = "gpio14"; 1048 function = "alt4"; 1049 bias-pull-up; 1050 }; 1051 pin-rts { 1052 pins = "gpio15"; 1053 function = "alt4"; 1054 bias-disable; 1055 }; 1056 }; 1057}; 1058 1059&rmem { 1060 #address-cells = <2>; 1061}; 1062 1063&cma { 1064 /* 1065 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1066 * that's not good enough for the BCM2711 as some devices can 1067 * only address the lower 1G of memory (ZONE_DMA). 1068 */ 1069 alloc-ranges = <0x0 0x00000000 0x40000000>; 1070}; 1071 1072&i2c0 { 1073 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1074 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1075}; 1076 1077&i2c1 { 1078 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1079 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1080}; 1081 1082&mailbox { 1083 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1084}; 1085 1086&sdhci { 1087 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1088}; 1089 1090&sdhost { 1091 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1092}; 1093 1094&spi { 1095 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1096}; 1097 1098&spi1 { 1099 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1100}; 1101 1102&spi2 { 1103 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1104}; 1105 1106&system_timer { 1107 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1111}; 1112 1113&txp { 1114 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1115}; 1116 1117&uart0 { 1118 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1119}; 1120 1121&uart1 { 1122 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1123}; 1124 1125&usb { 1126 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1127}; 1128 1129&vec { 1130 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1131}; 1132