18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef __ASM_ARC_SMP_H 78c2ecf20Sopenharmony_ci#define __ASM_ARC_SMP_H 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#ifdef CONFIG_SMP 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <linux/types.h> 128c2ecf20Sopenharmony_ci#include <linux/init.h> 138c2ecf20Sopenharmony_ci#include <linux/threads.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#define raw_smp_processor_id() (current_thread_info()->cpu) 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* including cpumask.h leads to cyclic deps hence this Forward declaration */ 188c2ecf20Sopenharmony_cistruct cpumask; 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci/* 218c2ecf20Sopenharmony_ci * APIs provided by arch SMP code to generic code 228c2ecf20Sopenharmony_ci */ 238c2ecf20Sopenharmony_ciextern void arch_send_call_function_single_ipi(int cpu); 248c2ecf20Sopenharmony_ciextern void arch_send_call_function_ipi_mask(const struct cpumask *mask); 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci/* 278c2ecf20Sopenharmony_ci * APIs provided by arch SMP code to rest of arch code 288c2ecf20Sopenharmony_ci */ 298c2ecf20Sopenharmony_ciextern void __init smp_init_cpus(void); 308c2ecf20Sopenharmony_ciextern void first_lines_of_secondary(void); 318c2ecf20Sopenharmony_ciextern const char *arc_platform_smp_cpuinfo(void); 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci/* 348c2ecf20Sopenharmony_ci * API expected BY platform smp code (FROM arch smp code) 358c2ecf20Sopenharmony_ci * 368c2ecf20Sopenharmony_ci * smp_ipi_irq_setup: 378c2ecf20Sopenharmony_ci * Takes @cpu and @hwirq to which the arch-common ISR is hooked up 388c2ecf20Sopenharmony_ci */ 398c2ecf20Sopenharmony_ciextern int smp_ipi_irq_setup(int cpu, irq_hw_number_t hwirq); 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci/* 428c2ecf20Sopenharmony_ci * struct plat_smp_ops - SMP callbacks provided by platform to ARC SMP 438c2ecf20Sopenharmony_ci * 448c2ecf20Sopenharmony_ci * @info: SoC SMP specific info for /proc/cpuinfo etc 458c2ecf20Sopenharmony_ci * @init_early_smp: A SMP specific h/w block can init itself 468c2ecf20Sopenharmony_ci * Could be common across platforms so not covered by 478c2ecf20Sopenharmony_ci * mach_desc->init_early() 488c2ecf20Sopenharmony_ci * @init_per_cpu: Called for each core so SMP h/w block driver can do 498c2ecf20Sopenharmony_ci * any needed setup per cpu (e.g. IPI request) 508c2ecf20Sopenharmony_ci * @cpu_kick: For Master to kickstart a cpu (optionally at a PC) 518c2ecf20Sopenharmony_ci * @ipi_send: To send IPI to a @cpu 528c2ecf20Sopenharmony_ci * @ips_clear: To clear IPI received at @irq 538c2ecf20Sopenharmony_ci */ 548c2ecf20Sopenharmony_cistruct plat_smp_ops { 558c2ecf20Sopenharmony_ci const char *info; 568c2ecf20Sopenharmony_ci void (*init_early_smp)(void); 578c2ecf20Sopenharmony_ci void (*init_per_cpu)(int cpu); 588c2ecf20Sopenharmony_ci void (*cpu_kick)(int cpu, unsigned long pc); 598c2ecf20Sopenharmony_ci void (*ipi_send)(int cpu); 608c2ecf20Sopenharmony_ci void (*ipi_clear)(int irq); 618c2ecf20Sopenharmony_ci}; 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci/* TBD: stop exporting it for direct population by platform */ 648c2ecf20Sopenharmony_ciextern struct plat_smp_ops plat_smp_ops; 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ci#else /* CONFIG_SMP */ 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_cistatic inline void smp_init_cpus(void) {} 698c2ecf20Sopenharmony_cistatic inline const char *arc_platform_smp_cpuinfo(void) 708c2ecf20Sopenharmony_ci{ 718c2ecf20Sopenharmony_ci return ""; 728c2ecf20Sopenharmony_ci} 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ci#endif /* !CONFIG_SMP */ 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci/* 778c2ecf20Sopenharmony_ci * ARC700 doesn't support atomic Read-Modify-Write ops. 788c2ecf20Sopenharmony_ci * Originally Interrupts had to be disabled around code to gaurantee atomicity. 798c2ecf20Sopenharmony_ci * The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops 808c2ecf20Sopenharmony_ci * based on retry-if-irq-in-atomic (with hardware assist). 818c2ecf20Sopenharmony_ci * However despite these, we provide the IRQ disabling variant 828c2ecf20Sopenharmony_ci * 838c2ecf20Sopenharmony_ci * (1) These insn were introduced only in 4.10 release. So for older released 848c2ecf20Sopenharmony_ci * support needed. 858c2ecf20Sopenharmony_ci * 868c2ecf20Sopenharmony_ci * (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be 878c2ecf20Sopenharmony_ci * gaurantted by the platform (not something which core handles). 888c2ecf20Sopenharmony_ci * Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ 898c2ecf20Sopenharmony_ci * disabling for atomicity. 908c2ecf20Sopenharmony_ci * 918c2ecf20Sopenharmony_ci * However exported spinlock API is not usable due to cyclic hdr deps 928c2ecf20Sopenharmony_ci * (even after system.h disintegration upstream) 938c2ecf20Sopenharmony_ci * asm/bitops.h -> linux/spinlock.h -> linux/preempt.h 948c2ecf20Sopenharmony_ci * -> linux/thread_info.h -> linux/bitops.h -> asm/bitops.h 958c2ecf20Sopenharmony_ci * 968c2ecf20Sopenharmony_ci * So the workaround is to use the lowest level arch spinlock API. 978c2ecf20Sopenharmony_ci * The exported spinlock API is smart enough to be NOP for !CONFIG_SMP, 988c2ecf20Sopenharmony_ci * but same is not true for ARCH backend, hence the need for 2 variants 998c2ecf20Sopenharmony_ci */ 1008c2ecf20Sopenharmony_ci#ifndef CONFIG_ARC_HAS_LLSC 1018c2ecf20Sopenharmony_ci 1028c2ecf20Sopenharmony_ci#include <linux/irqflags.h> 1038c2ecf20Sopenharmony_ci#ifdef CONFIG_SMP 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci#include <asm/spinlock.h> 1068c2ecf20Sopenharmony_ci 1078c2ecf20Sopenharmony_ciextern arch_spinlock_t smp_atomic_ops_lock; 1088c2ecf20Sopenharmony_ciextern arch_spinlock_t smp_bitops_lock; 1098c2ecf20Sopenharmony_ci 1108c2ecf20Sopenharmony_ci#define atomic_ops_lock(flags) do { \ 1118c2ecf20Sopenharmony_ci local_irq_save(flags); \ 1128c2ecf20Sopenharmony_ci arch_spin_lock(&smp_atomic_ops_lock); \ 1138c2ecf20Sopenharmony_ci} while (0) 1148c2ecf20Sopenharmony_ci 1158c2ecf20Sopenharmony_ci#define atomic_ops_unlock(flags) do { \ 1168c2ecf20Sopenharmony_ci arch_spin_unlock(&smp_atomic_ops_lock); \ 1178c2ecf20Sopenharmony_ci local_irq_restore(flags); \ 1188c2ecf20Sopenharmony_ci} while (0) 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci#define bitops_lock(flags) do { \ 1218c2ecf20Sopenharmony_ci local_irq_save(flags); \ 1228c2ecf20Sopenharmony_ci arch_spin_lock(&smp_bitops_lock); \ 1238c2ecf20Sopenharmony_ci} while (0) 1248c2ecf20Sopenharmony_ci 1258c2ecf20Sopenharmony_ci#define bitops_unlock(flags) do { \ 1268c2ecf20Sopenharmony_ci arch_spin_unlock(&smp_bitops_lock); \ 1278c2ecf20Sopenharmony_ci local_irq_restore(flags); \ 1288c2ecf20Sopenharmony_ci} while (0) 1298c2ecf20Sopenharmony_ci 1308c2ecf20Sopenharmony_ci#else /* !CONFIG_SMP */ 1318c2ecf20Sopenharmony_ci 1328c2ecf20Sopenharmony_ci#define atomic_ops_lock(flags) local_irq_save(flags) 1338c2ecf20Sopenharmony_ci#define atomic_ops_unlock(flags) local_irq_restore(flags) 1348c2ecf20Sopenharmony_ci 1358c2ecf20Sopenharmony_ci#define bitops_lock(flags) local_irq_save(flags) 1368c2ecf20Sopenharmony_ci#define bitops_unlock(flags) local_irq_restore(flags) 1378c2ecf20Sopenharmony_ci 1388c2ecf20Sopenharmony_ci#endif /* !CONFIG_SMP */ 1398c2ecf20Sopenharmony_ci 1408c2ecf20Sopenharmony_ci#endif /* !CONFIG_ARC_HAS_LLSC */ 1418c2ecf20Sopenharmony_ci 1428c2ecf20Sopenharmony_ci#endif 143