1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
7 *  Stack switching code can no longer reliably rely on the fact that
8 *  if we are NOT in user mode, stack is switched to kernel mode.
9 *  e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
10 *  it's prologue including stack switching from user mode
11 *
12 * Vineetg: Aug 28th 2008: Bug #94984
13 *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
14 *   Normally CPU does this automatically, however when doing FAKE rtie,
15 *   we also need to explicitly do this. The problem in macros
16 *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
17 *   was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
18 *
19 * Vineetg: May 5th 2008
20 *  -Modified CALLEE_REG save/restore macros to handle the fact that
21 *      r25 contains the kernel current task ptr
22 *  - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
23 *  - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
24 *      address Write back load ld.ab instead of seperate ld/add instn
25 *
26 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
27 */
28
29#ifndef __ASM_ARC_ENTRY_COMPACT_H
30#define __ASM_ARC_ENTRY_COMPACT_H
31
32#include <asm/asm-offsets.h>
33#include <asm/irqflags-compact.h>
34#include <asm/thread_info.h>	/* For THREAD_SIZE */
35
36/*--------------------------------------------------------------
37 * Switch to Kernel Mode stack if SP points to User Mode stack
38 *
39 * Entry   : r9 contains pre-IRQ/exception/trap status32
40 * Exit    : SP set to K mode stack
41 *           SP at the time of entry (K/U) saved @ pt_regs->sp
42 * Clobbers: r9
43 *-------------------------------------------------------------*/
44
45.macro SWITCH_TO_KERNEL_STK
46
47	/* User Mode when this happened ? Yes: Proceed to switch stack */
48	bbit1   r9, STATUS_U_BIT, 88f
49
50	/* OK we were already in kernel mode when this event happened, thus can
51	 * assume SP is kernel mode SP. _NO_ need to do any stack switching
52	 */
53
54#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
55	/* However....
56	 * If Level 2 Interrupts enabled, we may end up with a corner case:
57	 * 1. User Task executing
58	 * 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
59	 * 3. But before it could switch SP from USER to KERNEL stack
60	 *      a L2 IRQ "Interrupts" L1
61	 * Thay way although L2 IRQ happened in Kernel mode, stack is still
62	 * not switched.
63	 * To handle this, we may need to switch stack even if in kernel mode
64	 * provided SP has values in range of USER mode stack ( < 0x7000_0000 )
65	 */
66	brlo sp, VMALLOC_START, 88f
67
68	/* TODO: vineetg:
69	 * We need to be a bit more cautious here. What if a kernel bug in
70	 * L1 ISR, caused SP to go whaco (some small value which looks like
71	 * USER stk) and then we take L2 ISR.
72	 * Above brlo alone would treat it as a valid L1-L2 scenario
73	 * instead of shouting around
74	 * The only feasible way is to make sure this L2 happened in
75	 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
76	 * L1 ISR before it switches stack
77	 */
78
79#endif
80
81    /*------Intr/Ecxp happened in kernel mode, SP already setup ------ */
82	/* save it nevertheless @ pt_regs->sp for uniformity */
83
84	b.d	66f
85	st	sp, [sp, PT_sp - SZ_PT_REGS]
86
8788: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */
88
89	GET_CURR_TASK_ON_CPU   r9
90
91	/* With current tsk in r9, get it's kernel mode stack base */
92	GET_TSK_STACK_BASE  r9, r9
93
94	/* save U mode SP @ pt_regs->sp */
95	st	sp, [r9, PT_sp - SZ_PT_REGS]
96
97	/* final SP switch */
98	mov	sp, r9
9966:
100.endm
101
102/*------------------------------------------------------------
103 * "FAKE" a rtie to return from CPU Exception context
104 * This is to re-enable Exceptions within exception
105 * Look at EV_ProtV to see how this is actually used
106 *-------------------------------------------------------------*/
107
108.macro FAKE_RET_FROM_EXCPN
109
110	lr	r9, [status32]
111	bclr	r9, r9, STATUS_AE_BIT
112	or	r9, r9, (STATUS_E1_MASK|STATUS_E2_MASK)
113	sr	r9, [erstatus]
114	mov	r9, 55f
115	sr	r9, [eret]
116	rtie
11755:
118.endm
119
120/*--------------------------------------------------------------
121 * For early Exception/ISR Prologue, a core reg is temporarily needed to
122 * code the rest of prolog (stack switching). This is done by stashing
123 * it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
124 *
125 * Before saving the full regfile - this reg is restored back, only
126 * to be saved again on kernel mode stack, as part of pt_regs.
127 *-------------------------------------------------------------*/
128.macro PROLOG_FREEUP_REG	reg, mem
129#ifndef ARC_USE_SCRATCH_REG
130	sr  \reg, [ARC_REG_SCRATCH_DATA0]
131#else
132	st  \reg, [\mem]
133#endif
134.endm
135
136.macro PROLOG_RESTORE_REG	reg, mem
137#ifndef ARC_USE_SCRATCH_REG
138	lr  \reg, [ARC_REG_SCRATCH_DATA0]
139#else
140	ld  \reg, [\mem]
141#endif
142.endm
143
144/*--------------------------------------------------------------
145 * Exception Entry prologue
146 * -Switches stack to K mode (if not already)
147 * -Saves the register file
148 *
149 * After this it is safe to call the "C" handlers
150 *-------------------------------------------------------------*/
151.macro EXCEPTION_PROLOGUE
152
153	/* Need at least 1 reg to code the early exception prologue */
154	PROLOG_FREEUP_REG r9, @ex_saved_reg1
155
156	/* U/K mode at time of exception (stack not switched if already K) */
157	lr  r9, [erstatus]
158
159	/* ARC700 doesn't provide auto-stack switching */
160	SWITCH_TO_KERNEL_STK
161
162#ifdef CONFIG_ARC_CURR_IN_REG
163	/* Treat r25 as scratch reg (save on stack) and load with "current" */
164	PUSH    r25
165	GET_CURR_TASK_ON_CPU   r25
166#else
167	sub     sp, sp, 4
168#endif
169
170	st.a	r0, [sp, -8]    /* orig_r0 needed for syscall (skip ECR slot) */
171	sub	sp, sp, 4	/* skip pt_regs->sp, already saved above */
172
173	/* Restore r9 used to code the early prologue */
174	PROLOG_RESTORE_REG  r9, @ex_saved_reg1
175
176	/* now we are ready to save the regfile */
177	SAVE_R0_TO_R12
178	PUSH	gp
179	PUSH	fp
180	PUSH	blink
181	PUSHAX	eret
182	PUSHAX	erstatus
183	PUSH	lp_count
184	PUSHAX	lp_end
185	PUSHAX	lp_start
186	PUSHAX	erbta
187
188	lr	r10, [ecr]
189	st      r10, [sp, PT_event]    /* EV_Trap expects r10 to have ECR */
190.endm
191
192/*--------------------------------------------------------------
193 * Restore all registers used by system call or Exceptions
194 * SP should always be pointing to the next free stack element
195 * when entering this macro.
196 *
197 * NOTE:
198 *
199 * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
200 * for memory load operations. If used in that way interrupts are deffered
201 * by hardware and that is not good.
202 *-------------------------------------------------------------*/
203.macro EXCEPTION_EPILOGUE
204
205	POPAX	erbta
206	POPAX	lp_start
207	POPAX	lp_end
208
209	POP	r9
210	mov	lp_count, r9	;LD to lp_count is not allowed
211
212	POPAX	erstatus
213	POPAX	eret
214	POP	blink
215	POP	fp
216	POP	gp
217	RESTORE_R12_TO_R0
218
219#ifdef CONFIG_ARC_CURR_IN_REG
220	ld	r25, [sp, 12]
221#endif
222	ld  sp, [sp] /* restore original sp */
223	/* orig_r0, ECR, user_r25 skipped automatically */
224.endm
225
226/* Dummy ECR values for Interrupts */
227#define event_IRQ1		0x0031abcd
228#define event_IRQ2		0x0032abcd
229
230.macro INTERRUPT_PROLOGUE  LVL
231
232	/* free up r9 as scratchpad */
233	PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg
234
235	/* Which mode (user/kernel) was the system in when intr occurred */
236	lr  r9, [status32_l\LVL\()]
237
238	SWITCH_TO_KERNEL_STK
239
240#ifdef CONFIG_ARC_CURR_IN_REG
241	/* Treat r25 as scratch reg (save on stack) and load with "current" */
242	PUSH    r25
243	GET_CURR_TASK_ON_CPU   r25
244#else
245	sub     sp, sp, 4
246#endif
247
248	PUSH	0x003\LVL\()abcd    /* Dummy ECR */
249	sub	sp, sp, 8	    /* skip orig_r0 (not needed)
250				       skip pt_regs->sp, already saved above */
251
252	/* Restore r9 used to code the early prologue */
253	PROLOG_RESTORE_REG  r9, @int\LVL\()_saved_reg
254
255	SAVE_R0_TO_R12
256	PUSH	gp
257	PUSH	fp
258	PUSH	blink
259	PUSH	ilink\LVL\()
260	PUSHAX	status32_l\LVL\()
261	PUSH	lp_count
262	PUSHAX	lp_end
263	PUSHAX	lp_start
264	PUSHAX	bta_l\LVL\()
265
266.endm
267
268/*--------------------------------------------------------------
269 * Restore all registers used by interrupt handlers.
270 *
271 * NOTE:
272 *
273 * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
274 * for memory load operations. If used in that way interrupts are deffered
275 * by hardware and that is not good.
276 *-------------------------------------------------------------*/
277.macro INTERRUPT_EPILOGUE  LVL
278
279	POPAX	bta_l\LVL\()
280	POPAX	lp_start
281	POPAX	lp_end
282
283	POP	r9
284	mov	lp_count, r9	;LD to lp_count is not allowed
285
286	POPAX	status32_l\LVL\()
287	POP	ilink\LVL\()
288	POP	blink
289	POP	fp
290	POP	gp
291	RESTORE_R12_TO_R0
292
293#ifdef CONFIG_ARC_CURR_IN_REG
294	ld	r25, [sp, 12]
295#endif
296	ld  sp, [sp] /* restore original sp */
297	/* orig_r0, ECR, user_r25 skipped automatically */
298.endm
299
300/* Get thread_info of "current" tsk */
301.macro GET_CURR_THR_INFO_FROM_SP  reg
302	bic \reg, sp, (THREAD_SIZE - 1)
303.endm
304
305/* Get CPU-ID of this core */
306.macro  GET_CPU_ID  reg
307	lr  \reg, [identity]
308	lsr \reg, \reg, 8
309	bmsk \reg, \reg, 7
310.endm
311
312#endif  /* __ASM_ARC_ENTRY_COMPACT_H */
313