18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci/* 78c2ecf20Sopenharmony_ci * Skeleton device tree; the bare minimum needed to boot; just include and 88c2ecf20Sopenharmony_ci * add a compatible value. 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/ { 128c2ecf20Sopenharmony_ci compatible = "snps,arc"; 138c2ecf20Sopenharmony_ci #address-cells = <1>; 148c2ecf20Sopenharmony_ci #size-cells = <1>; 158c2ecf20Sopenharmony_ci chosen { }; 168c2ecf20Sopenharmony_ci aliases { }; 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci cpus { 198c2ecf20Sopenharmony_ci #address-cells = <1>; 208c2ecf20Sopenharmony_ci #size-cells = <0>; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci cpu@0 { 238c2ecf20Sopenharmony_ci device_type = "cpu"; 248c2ecf20Sopenharmony_ci compatible = "snps,arc770d"; 258c2ecf20Sopenharmony_ci reg = <0>; 268c2ecf20Sopenharmony_ci clocks = <&core_clk>; 278c2ecf20Sopenharmony_ci }; 288c2ecf20Sopenharmony_ci }; 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci /* TIMER0 with interrupt for clockevent */ 318c2ecf20Sopenharmony_ci timer0 { 328c2ecf20Sopenharmony_ci compatible = "snps,arc-timer"; 338c2ecf20Sopenharmony_ci interrupts = <3>; 348c2ecf20Sopenharmony_ci interrupt-parent = <&core_intc>; 358c2ecf20Sopenharmony_ci clocks = <&core_clk>; 368c2ecf20Sopenharmony_ci }; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci /* TIMER1 for free running clocksource */ 398c2ecf20Sopenharmony_ci timer1 { 408c2ecf20Sopenharmony_ci compatible = "snps,arc-timer"; 418c2ecf20Sopenharmony_ci clocks = <&core_clk>; 428c2ecf20Sopenharmony_ci }; 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ci memory { 458c2ecf20Sopenharmony_ci device_type = "memory"; 468c2ecf20Sopenharmony_ci reg = <0x80000000 0x10000000>; /* 256M */ 478c2ecf20Sopenharmony_ci }; 488c2ecf20Sopenharmony_ci}; 49