18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * include/asm-alpha/cache.h 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci#ifndef __ARCH_ALPHA_CACHE_H 68c2ecf20Sopenharmony_ci#define __ARCH_ALPHA_CACHE_H 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci/* Bytes per L1 (data) cache line. */ 108c2ecf20Sopenharmony_ci#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6) 118c2ecf20Sopenharmony_ci# define L1_CACHE_BYTES 64 128c2ecf20Sopenharmony_ci# define L1_CACHE_SHIFT 6 138c2ecf20Sopenharmony_ci#else 148c2ecf20Sopenharmony_ci/* Both EV4 and EV5 are write-through, read-allocate, 158c2ecf20Sopenharmony_ci direct-mapped, physical. 168c2ecf20Sopenharmony_ci*/ 178c2ecf20Sopenharmony_ci# define L1_CACHE_BYTES 32 188c2ecf20Sopenharmony_ci# define L1_CACHE_SHIFT 5 198c2ecf20Sopenharmony_ci#endif 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#define SMP_CACHE_BYTES L1_CACHE_BYTES 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#endif 24