18c2ecf20Sopenharmony_ci.. SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ci========================= 48c2ecf20Sopenharmony_ciMPIC interrupt controller 58c2ecf20Sopenharmony_ci========================= 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciDevice types supported: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0 108c2ecf20Sopenharmony_ci - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciOnly one MPIC instance, of any type, may be instantiated. The created 138c2ecf20Sopenharmony_ciMPIC will act as the system interrupt controller, connecting to each 148c2ecf20Sopenharmony_civcpu's interrupt inputs. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciGroups: 178c2ecf20Sopenharmony_ci KVM_DEV_MPIC_GRP_MISC 188c2ecf20Sopenharmony_ci Attributes: 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit) 218c2ecf20Sopenharmony_ci Base address of the 256 KiB MPIC register space. Must be 228c2ecf20Sopenharmony_ci naturally aligned. A value of zero disables the mapping. 238c2ecf20Sopenharmony_ci Reset value is zero. 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit) 268c2ecf20Sopenharmony_ci Access an MPIC register, as if the access were made from the guest. 278c2ecf20Sopenharmony_ci "attr" is the byte offset into the MPIC register space. Accesses 288c2ecf20Sopenharmony_ci must be 4-byte aligned. 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci MSIs may be signaled by using this attribute group to write 318c2ecf20Sopenharmony_ci to the relevant MSIIR. 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit) 348c2ecf20Sopenharmony_ci IRQ input line for each standard openpic source. 0 is inactive and 1 358c2ecf20Sopenharmony_ci is active, regardless of interrupt sense. 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci For edge-triggered interrupts: Writing 1 is considered an activating 388c2ecf20Sopenharmony_ci edge, and writing 0 is ignored. Reading returns 1 if a previously 398c2ecf20Sopenharmony_ci signaled edge has not been acknowledged, and 0 otherwise. 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci "attr" is the IRQ number. IRQ numbers for standard sources are the 428c2ecf20Sopenharmony_ci byte offset of the relevant IVPR from EIVPR0, divided by 32. 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ciIRQ Routing: 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci The MPIC emulation supports IRQ routing. Only a single MPIC device can 478c2ecf20Sopenharmony_ci be instantiated. Once that device has been created, it's available as 488c2ecf20Sopenharmony_ci irqchip id 0. 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci This irqchip 0 has 256 interrupt pins, which expose the interrupts in 518c2ecf20Sopenharmony_ci the main array of interrupt sources (a.k.a. "SRC" interrupts). 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci The numbering is the same as the MPIC device tree binding -- based on 548c2ecf20Sopenharmony_ci the register offset from the beginning of the sources array, without 558c2ecf20Sopenharmony_ci regard to any subdivisions in chip documentation such as "internal" 568c2ecf20Sopenharmony_ci or "external" interrupts. 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci Access to non-SRC interrupts is not implemented through IRQ routing mechanisms. 59