18c2ecf20Sopenharmony_ci.. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ci.. _image-process-controls:
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58c2ecf20Sopenharmony_ci*******************************
68c2ecf20Sopenharmony_ciImage Process Control Reference
78c2ecf20Sopenharmony_ci*******************************
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ciThe Image Process control class is intended for low-level control of
108c2ecf20Sopenharmony_ciimage processing functions. Unlike ``V4L2_CID_IMAGE_SOURCE_CLASS``, the
118c2ecf20Sopenharmony_cicontrols in this class affect processing the image, and do not control
128c2ecf20Sopenharmony_cicapturing of it.
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158c2ecf20Sopenharmony_ci.. _image-process-control-id:
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178c2ecf20Sopenharmony_ciImage Process Control IDs
188c2ecf20Sopenharmony_ci=========================
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci``V4L2_CID_IMAGE_PROC_CLASS (class)``
218c2ecf20Sopenharmony_ci    The IMAGE_PROC class descriptor.
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci``V4L2_CID_LINK_FREQ (integer menu)``
248c2ecf20Sopenharmony_ci    Data bus frequency. Together with the media bus pixel code, bus type
258c2ecf20Sopenharmony_ci    (clock cycles per sample), the data bus frequency defines the pixel
268c2ecf20Sopenharmony_ci    rate (``V4L2_CID_PIXEL_RATE``) in the pixel array (or possibly
278c2ecf20Sopenharmony_ci    elsewhere, if the device is not an image sensor). The frame rate can
288c2ecf20Sopenharmony_ci    be calculated from the pixel clock, image width and height and
298c2ecf20Sopenharmony_ci    horizontal and vertical blanking. While the pixel rate control may
308c2ecf20Sopenharmony_ci    be defined elsewhere than in the subdev containing the pixel array,
318c2ecf20Sopenharmony_ci    the frame rate cannot be obtained from that information. This is
328c2ecf20Sopenharmony_ci    because only on the pixel array it can be assumed that the vertical
338c2ecf20Sopenharmony_ci    and horizontal blanking information is exact: no other blanking is
348c2ecf20Sopenharmony_ci    allowed in the pixel array. The selection of frame rate is performed
358c2ecf20Sopenharmony_ci    by selecting the desired horizontal and vertical blanking. The unit
368c2ecf20Sopenharmony_ci    of this control is Hz.
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci``V4L2_CID_PIXEL_RATE (64-bit integer)``
398c2ecf20Sopenharmony_ci    Pixel rate in the source pads of the subdev. This control is
408c2ecf20Sopenharmony_ci    read-only and its unit is pixels / second.
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci``V4L2_CID_TEST_PATTERN (menu)``
438c2ecf20Sopenharmony_ci    Some capture/display/sensor devices have the capability to generate
448c2ecf20Sopenharmony_ci    test pattern images. These hardware specific test patterns can be
458c2ecf20Sopenharmony_ci    used to test if a device is working properly.
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci``V4L2_CID_DEINTERLACING_MODE (menu)``
488c2ecf20Sopenharmony_ci    The video deinterlacing mode (such as Bob, Weave, ...). The menu items are
498c2ecf20Sopenharmony_ci    driver specific and are documented in :ref:`uapi-v4l-drivers`.
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ci``V4L2_CID_DIGITAL_GAIN (integer)``
528c2ecf20Sopenharmony_ci    Digital gain is the value by which all colour components
538c2ecf20Sopenharmony_ci    are multiplied by. Typically the digital gain applied is the
548c2ecf20Sopenharmony_ci    control value divided by e.g. 0x100, meaning that to get no
558c2ecf20Sopenharmony_ci    digital gain the control value needs to be 0x100. The no-gain
568c2ecf20Sopenharmony_ci    configuration is also typically the default.
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