18c2ecf20Sopenharmony_ci=============================================
28c2ecf20Sopenharmony_ciBroadcom Starfighter 2 Ethernet switch driver
38c2ecf20Sopenharmony_ci=============================================
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ciBroadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
68c2ecf20Sopenharmony_cideployed in the following products:
78c2ecf20Sopenharmony_ci
88c2ecf20Sopenharmony_ci- xDSL gateways such as BCM63138
98c2ecf20Sopenharmony_ci- streaming/multimedia Set Top Box such as BCM7445
108c2ecf20Sopenharmony_ci- Cable Modem/residential gateways such as BCM7145/BCM3390
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ciThe switch is typically deployed in a configuration involving between 5 to 13
138c2ecf20Sopenharmony_ciports, offering a range of built-in and customizable interfaces:
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci- single integrated Gigabit PHY
168c2ecf20Sopenharmony_ci- quad integrated Gigabit PHY
178c2ecf20Sopenharmony_ci- quad external Gigabit PHY w/ MDIO multiplexer
188c2ecf20Sopenharmony_ci- integrated MoCA PHY
198c2ecf20Sopenharmony_ci- several external MII/RevMII/GMII/RGMII interfaces
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ciThe switch also supports specific congestion control features which allow MoCA
228c2ecf20Sopenharmony_cifail-over not to lose packets during a MoCA role re-election, as well as out of
238c2ecf20Sopenharmony_ciband back-pressure to the host CPU network interface when downstream interfaces
248c2ecf20Sopenharmony_ciare connected at a lower speed.
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ciThe switch hardware block is typically interfaced using MMIO accesses and
278c2ecf20Sopenharmony_cicontains a bunch of sub-blocks/registers:
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci- ``SWITCH_CORE``: common switch registers
308c2ecf20Sopenharmony_ci- ``SWITCH_REG``: external interfaces switch register
318c2ecf20Sopenharmony_ci- ``SWITCH_MDIO``: external MDIO bus controller (there is another one in SWITCH_CORE,
328c2ecf20Sopenharmony_ci  which is used for indirect PHY accesses)
338c2ecf20Sopenharmony_ci- ``SWITCH_INDIR_RW``: 64-bits wide register helper block
348c2ecf20Sopenharmony_ci- ``SWITCH_INTRL2_0/1``: Level-2 interrupt controllers
358c2ecf20Sopenharmony_ci- ``SWITCH_ACB``: Admission control block
368c2ecf20Sopenharmony_ci- ``SWITCH_FCB``: Fail-over control block
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ciImplementation details
398c2ecf20Sopenharmony_ci======================
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_ciThe driver is located in ``drivers/net/dsa/bcm_sf2.c`` and is implemented as a DSA
428c2ecf20Sopenharmony_cidriver; see ``Documentation/networking/dsa/dsa.rst`` for details on the subsystem
438c2ecf20Sopenharmony_ciand what it provides.
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_ciThe SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag
468c2ecf20Sopenharmony_ciwhich gets inserted by the switch for every packet forwarded to the CPU
478c2ecf20Sopenharmony_ciinterface, conversely, the CPU network interface should insert a similar tag for
488c2ecf20Sopenharmony_cipackets entering the CPU port. The tag format is described in
498c2ecf20Sopenharmony_ci``net/dsa/tag_brcm.c``.
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ciOverall, the SF2 driver is a fairly regular DSA driver; there are a few
528c2ecf20Sopenharmony_cispecifics covered below.
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_ciDevice Tree probing
558c2ecf20Sopenharmony_ci-------------------
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ciThe DSA platform device driver is probed using a specific compatible string
588c2ecf20Sopenharmony_ciprovided in ``net/dsa/dsa.c``. The reason for that is because the DSA subsystem gets
598c2ecf20Sopenharmony_ciregistered as a platform device driver currently. DSA will provide the needed
608c2ecf20Sopenharmony_cidevice_node pointers which are then accessible by the switch driver setup
618c2ecf20Sopenharmony_cifunction to setup resources such as register ranges and interrupts. This
628c2ecf20Sopenharmony_cicurrently works very well because none of the of_* functions utilized by the
638c2ecf20Sopenharmony_cidriver require a struct device to be bound to a struct device_node, but things
648c2ecf20Sopenharmony_cimay change in the future.
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ciMDIO indirect accesses
678c2ecf20Sopenharmony_ci----------------------
688c2ecf20Sopenharmony_ci
698c2ecf20Sopenharmony_ciDue to a limitation in how Broadcom switches have been designed, external
708c2ecf20Sopenharmony_ciBroadcom switches connected to a SF2 require the use of the DSA slave MDIO bus
718c2ecf20Sopenharmony_ciin order to properly configure them. By default, the SF2 pseudo-PHY address, and
728c2ecf20Sopenharmony_cian external switch pseudo-PHY address will both be snooping for incoming MDIO
738c2ecf20Sopenharmony_citransactions, since they are at the same address (30), resulting in some kind of
748c2ecf20Sopenharmony_ci"double" programming. Using DSA, and setting ``ds->phys_mii_mask`` accordingly, we
758c2ecf20Sopenharmony_ciselectively divert reads and writes towards external Broadcom switches
768c2ecf20Sopenharmony_cipseudo-PHY addresses. Newer revisions of the SF2 hardware have introduced a
778c2ecf20Sopenharmony_ciconfigurable pseudo-PHY address which circumvents the initial design limitation.
788c2ecf20Sopenharmony_ci
798c2ecf20Sopenharmony_ciMultimedia over CoAxial (MoCA) interfaces
808c2ecf20Sopenharmony_ci-----------------------------------------
818c2ecf20Sopenharmony_ci
828c2ecf20Sopenharmony_ciMoCA interfaces are fairly specific and require the use of a firmware blob which
838c2ecf20Sopenharmony_cigets loaded onto the MoCA processor(s) for packet processing. The switch
848c2ecf20Sopenharmony_cihardware contains logic which will assert/de-assert link states accordingly for
858c2ecf20Sopenharmony_cithe MoCA interface whenever the MoCA coaxial cable gets disconnected or the
868c2ecf20Sopenharmony_cifirmware gets reloaded. The SF2 driver relies on such events to properly set its
878c2ecf20Sopenharmony_ciMoCA interface carrier state and properly report this to the networking stack.
888c2ecf20Sopenharmony_ci
898c2ecf20Sopenharmony_ciThe MoCA interfaces are supported using the PHY library's fixed PHY/emulated PHY
908c2ecf20Sopenharmony_cidevice and the switch driver registers a ``fixed_link_update`` callback for such
918c2ecf20Sopenharmony_ciPHYs which reflects the link state obtained from the interrupt handler.
928c2ecf20Sopenharmony_ci
938c2ecf20Sopenharmony_ci
948c2ecf20Sopenharmony_ciPower Management
958c2ecf20Sopenharmony_ci----------------
968c2ecf20Sopenharmony_ci
978c2ecf20Sopenharmony_ciWhenever possible, the SF2 driver tries to minimize the overall switch power
988c2ecf20Sopenharmony_ciconsumption by applying a combination of:
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ci- turning off internal buffers/memories
1018c2ecf20Sopenharmony_ci- disabling packet processing logic
1028c2ecf20Sopenharmony_ci- putting integrated PHYs in IDDQ/low-power
1038c2ecf20Sopenharmony_ci- reducing the switch core clock based on the active port count
1048c2ecf20Sopenharmony_ci- enabling and advertising EEE
1058c2ecf20Sopenharmony_ci- turning off RGMII data processing logic when the link goes down
1068c2ecf20Sopenharmony_ci
1078c2ecf20Sopenharmony_ciWake-on-LAN
1088c2ecf20Sopenharmony_ci-----------
1098c2ecf20Sopenharmony_ci
1108c2ecf20Sopenharmony_ciWake-on-LAN is currently implemented by utilizing the host processor Ethernet
1118c2ecf20Sopenharmony_ciMAC controller wake-on logic. Whenever Wake-on-LAN is requested, an intersection
1128c2ecf20Sopenharmony_cibetween the user request and the supported host Ethernet interface WoL
1138c2ecf20Sopenharmony_cicapabilities is done and the intersection result gets configured. During
1148c2ecf20Sopenharmony_cisystem-wide suspend/resume, only ports not participating in Wake-on-LAN are
1158c2ecf20Sopenharmony_cidisabled.
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