18c2ecf20Sopenharmony_ci================ 28c2ecf20Sopenharmony_ciThe I2C Protocol 38c2ecf20Sopenharmony_ci================ 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciThis document describes the I2C protocol. Or will, when it is finished :-) 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciKey to symbols 88c2ecf20Sopenharmony_ci============== 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci=============== ============================================================= 118c2ecf20Sopenharmony_ciS Start condition 128c2ecf20Sopenharmony_ciP Stop condition 138c2ecf20Sopenharmony_ciRd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0. 148c2ecf20Sopenharmony_ciA, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit 158c2ecf20Sopenharmony_ciAddr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to 168c2ecf20Sopenharmony_ci get a 10 bit I2C address. 178c2ecf20Sopenharmony_ciComm (8 bits) Command byte, a data byte which often selects a register on 188c2ecf20Sopenharmony_ci the device. 198c2ecf20Sopenharmony_ciData (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh 208c2ecf20Sopenharmony_ci for 16 bit data. 218c2ecf20Sopenharmony_ciCount (8 bits) A data byte containing the length of a block operation. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci[..] Data sent by I2C device, as opposed to data sent by the 248c2ecf20Sopenharmony_ci host adapter. 258c2ecf20Sopenharmony_ci=============== ============================================================= 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciSimple send transaction 298c2ecf20Sopenharmony_ci======================= 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ciImplemented by i2c_master_send():: 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ciSimple receive transaction 378c2ecf20Sopenharmony_ci========================== 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ciImplemented by i2c_master_recv():: 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_ciCombined transactions 458c2ecf20Sopenharmony_ci===================== 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ciImplemented by i2c_transfer(). 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ciThey are just like the above transactions, but instead of a stop 508c2ecf20Sopenharmony_cicondition P a start condition S is sent and the transaction continues. 518c2ecf20Sopenharmony_ciAn example of a byte read, followed by a byte write:: 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ciModified transactions 578c2ecf20Sopenharmony_ci===================== 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ciThe following modifications to the I2C protocol can also be generated by 608c2ecf20Sopenharmony_cisetting these flags for I2C messages. With the exception of I2C_M_NOSTART, they 618c2ecf20Sopenharmony_ciare usually only needed to work around device issues: 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ciI2C_M_IGNORE_NAK: 648c2ecf20Sopenharmony_ci Normally message is interrupted immediately if there is [NA] from the 658c2ecf20Sopenharmony_ci client. Setting this flag treats any [NA] as [A], and all of 668c2ecf20Sopenharmony_ci message is sent. 678c2ecf20Sopenharmony_ci These messages may still fail to SCL lo->hi timeout. 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ciI2C_M_NO_RD_ACK: 708c2ecf20Sopenharmony_ci In a read message, master A/NA bit is skipped. 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ciI2C_M_NOSTART: 738c2ecf20Sopenharmony_ci In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some 748c2ecf20Sopenharmony_ci point. For example, setting I2C_M_NOSTART on the second partial message 758c2ecf20Sopenharmony_ci generates something like:: 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_ci S Addr Rd [A] [Data] NA Data [A] P 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci If you set the I2C_M_NOSTART variable for the first partial message, 808c2ecf20Sopenharmony_ci we do not generate Addr, but we do generate the start condition S. 818c2ecf20Sopenharmony_ci This will probably confuse all other clients on your bus, so don't 828c2ecf20Sopenharmony_ci try this. 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ci This is often used to gather transmits from multiple data buffers in 858c2ecf20Sopenharmony_ci system memory into something that appears as a single transfer to the 868c2ecf20Sopenharmony_ci I2C device but may also be used between direction changes by some 878c2ecf20Sopenharmony_ci rare devices. 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ciI2C_M_REV_DIR_ADDR: 908c2ecf20Sopenharmony_ci This toggles the Rd/Wr flag. That is, if you want to do a write, but 918c2ecf20Sopenharmony_ci need to emit an Rd instead of a Wr, or vice versa, you set this 928c2ecf20Sopenharmony_ci flag. For example:: 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_ci S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ciI2C_M_STOP: 978c2ecf20Sopenharmony_ci Force a stop condition (P) after the message. Some I2C related protocols 988c2ecf20Sopenharmony_ci like SCCB require that. Normally, you really don't want to get interrupted 998c2ecf20Sopenharmony_ci between the messages of one transfer. 100