18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci%YAML 1.2 38c2ecf20Sopenharmony_ci--- 48c2ecf20Sopenharmony_ci$id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml# 58c2ecf20Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_cititle: ARM AMBA Primecell SP805 Watchdog 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cimaintainers: 108c2ecf20Sopenharmony_ci - Viresh Kumar <vireshk@kernel.org> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_cidescription: |+ 138c2ecf20Sopenharmony_ci The Arm SP805 IP implements a watchdog device, which triggers an interrupt 148c2ecf20Sopenharmony_ci after a configurable time period. If that interrupt has not been serviced 158c2ecf20Sopenharmony_ci when the next interrupt would be triggered, the reset signal is asserted. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciallOf: 188c2ecf20Sopenharmony_ci - $ref: /schemas/watchdog/watchdog.yaml# 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci# Need a custom select here or 'arm,primecell' will match on lots of nodes 218c2ecf20Sopenharmony_ciselect: 228c2ecf20Sopenharmony_ci properties: 238c2ecf20Sopenharmony_ci compatible: 248c2ecf20Sopenharmony_ci contains: 258c2ecf20Sopenharmony_ci const: arm,sp805 268c2ecf20Sopenharmony_ci required: 278c2ecf20Sopenharmony_ci - compatible 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ciproperties: 308c2ecf20Sopenharmony_ci compatible: 318c2ecf20Sopenharmony_ci items: 328c2ecf20Sopenharmony_ci - const: arm,sp805 338c2ecf20Sopenharmony_ci - const: arm,primecell 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci interrupts: 368c2ecf20Sopenharmony_ci maxItems: 1 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci reg: 398c2ecf20Sopenharmony_ci maxItems: 1 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci clocks: 428c2ecf20Sopenharmony_ci description: | 438c2ecf20Sopenharmony_ci Clocks driving the watchdog timer hardware. The first clock is used 448c2ecf20Sopenharmony_ci for the actual watchdog counter. The second clock drives the register 458c2ecf20Sopenharmony_ci interface. 468c2ecf20Sopenharmony_ci minItems: 2 478c2ecf20Sopenharmony_ci maxItems: 2 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci clock-names: 508c2ecf20Sopenharmony_ci items: 518c2ecf20Sopenharmony_ci - const: wdog_clk 528c2ecf20Sopenharmony_ci - const: apb_pclk 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_cirequired: 558c2ecf20Sopenharmony_ci - compatible 568c2ecf20Sopenharmony_ci - reg 578c2ecf20Sopenharmony_ci - clocks 588c2ecf20Sopenharmony_ci - clock-names 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ciunevaluatedProperties: false 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ciexamples: 638c2ecf20Sopenharmony_ci - | 648c2ecf20Sopenharmony_ci #include <dt-bindings/interrupt-controller/arm-gic.h> 658c2ecf20Sopenharmony_ci watchdog@66090000 { 668c2ecf20Sopenharmony_ci compatible = "arm,sp805", "arm,primecell"; 678c2ecf20Sopenharmony_ci reg = <0x66090000 0x1000>; 688c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; 698c2ecf20Sopenharmony_ci clocks = <&wdt_clk>, <&apb_pclk>; 708c2ecf20Sopenharmony_ci clock-names = "wdog_clk", "apb_pclk"; 718c2ecf20Sopenharmony_ci }; 72