18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci%YAML 1.2
38c2ecf20Sopenharmony_ci---
48c2ecf20Sopenharmony_ci$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
58c2ecf20Sopenharmony_ci$schema: "http://devicetree.org/meta-schemas/core.yaml#"
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_cititle: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_cimaintainers:
108c2ecf20Sopenharmony_ci  - Roger Quadros <rogerq@ti.com>
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ciproperties:
138c2ecf20Sopenharmony_ci  compatible:
148c2ecf20Sopenharmony_ci    items:
158c2ecf20Sopenharmony_ci      - const: ti,j721e-usb
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci  reg:
188c2ecf20Sopenharmony_ci    description: module registers
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci  power-domains:
218c2ecf20Sopenharmony_ci    description:
228c2ecf20Sopenharmony_ci      PM domain provider node and an args specifier containing
238c2ecf20Sopenharmony_ci      the USB device id value. See,
248c2ecf20Sopenharmony_ci      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci  clocks:
278c2ecf20Sopenharmony_ci    description: Clock phandles to usb2_refclk and lpm_clk
288c2ecf20Sopenharmony_ci    minItems: 2
298c2ecf20Sopenharmony_ci    maxItems: 2
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ci  clock-names:
328c2ecf20Sopenharmony_ci    items:
338c2ecf20Sopenharmony_ci      - const: ref
348c2ecf20Sopenharmony_ci      - const: lpm
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ci  ti,usb2-only:
378c2ecf20Sopenharmony_ci    description:
388c2ecf20Sopenharmony_ci      If present, it restricts the controller to USB2.0 mode of
398c2ecf20Sopenharmony_ci      operation. Must be present if USB3 PHY is not available
408c2ecf20Sopenharmony_ci      for USB.
418c2ecf20Sopenharmony_ci    type: boolean
428c2ecf20Sopenharmony_ci
438c2ecf20Sopenharmony_ci  ti,vbus-divider:
448c2ecf20Sopenharmony_ci    description:
458c2ecf20Sopenharmony_ci      Should be present if USB VBUS line is connected to the
468c2ecf20Sopenharmony_ci      VBUS pin of the SoC via a 1/3 voltage divider.
478c2ecf20Sopenharmony_ci    type: boolean
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci  assigned-clocks:
508c2ecf20Sopenharmony_ci    maxItems: 1
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci  assigned-clock-parents:
538c2ecf20Sopenharmony_ci    maxItems: 1
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ci  '#address-cells':
568c2ecf20Sopenharmony_ci    const: 2
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci  '#size-cells':
598c2ecf20Sopenharmony_ci    const: 2
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_cipatternProperties:
628c2ecf20Sopenharmony_ci  "^usb@":
638c2ecf20Sopenharmony_ci    type: object
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_cirequired:
668c2ecf20Sopenharmony_ci  - compatible
678c2ecf20Sopenharmony_ci  - reg
688c2ecf20Sopenharmony_ci  - power-domains
698c2ecf20Sopenharmony_ci  - clocks
708c2ecf20Sopenharmony_ci  - clock-names
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ciadditionalProperties: false
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_ciexamples:
758c2ecf20Sopenharmony_ci  - |
768c2ecf20Sopenharmony_ci    #include <dt-bindings/soc/ti,sci_pm_domain.h>
778c2ecf20Sopenharmony_ci    #include <dt-bindings/interrupt-controller/arm-gic.h>
788c2ecf20Sopenharmony_ci
798c2ecf20Sopenharmony_ci    bus {
808c2ecf20Sopenharmony_ci        #address-cells = <2>;
818c2ecf20Sopenharmony_ci        #size-cells = <2>;
828c2ecf20Sopenharmony_ci
838c2ecf20Sopenharmony_ci        cdns_usb@4104000 {
848c2ecf20Sopenharmony_ci            compatible = "ti,j721e-usb";
858c2ecf20Sopenharmony_ci            reg = <0x00 0x4104000 0x00 0x100>;
868c2ecf20Sopenharmony_ci            power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
878c2ecf20Sopenharmony_ci            clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
888c2ecf20Sopenharmony_ci            clock-names = "ref", "lpm";
898c2ecf20Sopenharmony_ci            assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
908c2ecf20Sopenharmony_ci            assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
918c2ecf20Sopenharmony_ci            #address-cells = <2>;
928c2ecf20Sopenharmony_ci            #size-cells = <2>;
938c2ecf20Sopenharmony_ci
948c2ecf20Sopenharmony_ci            usb@6000000 {
958c2ecf20Sopenharmony_ci                  compatible = "cdns,usb3";
968c2ecf20Sopenharmony_ci                  reg = <0x00 0x6000000 0x00 0x10000>,
978c2ecf20Sopenharmony_ci                        <0x00 0x6010000 0x00 0x10000>,
988c2ecf20Sopenharmony_ci                        <0x00 0x6020000 0x00 0x10000>;
998c2ecf20Sopenharmony_ci                  reg-names = "otg", "xhci", "dev";
1008c2ecf20Sopenharmony_ci                  interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
1018c2ecf20Sopenharmony_ci                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
1028c2ecf20Sopenharmony_ci                               <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
1038c2ecf20Sopenharmony_ci                  interrupt-names = "host",
1048c2ecf20Sopenharmony_ci                                    "peripheral",
1058c2ecf20Sopenharmony_ci                                    "otg";
1068c2ecf20Sopenharmony_ci                  maximum-speed = "super-speed";
1078c2ecf20Sopenharmony_ci                  dr_mode = "otg";
1088c2ecf20Sopenharmony_ci            };
1098c2ecf20Sopenharmony_ci        };
1108c2ecf20Sopenharmony_ci    };
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