18c2ecf20Sopenharmony_ciMT8173 xHCI 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe device node for Mediatek SOC USB3.0 host controller 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciThere are two scenarios: the first one only supports xHCI driver; 68c2ecf20Sopenharmony_cithe second one supports dual-role mode, and the host is based on xHCI 78c2ecf20Sopenharmony_cidriver. Take account of backward compatibility, we divide bindings 88c2ecf20Sopenharmony_ciinto two parts. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci1st: only supports xHCI driver 118c2ecf20Sopenharmony_ci------------------------------------------------------------------------ 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciRequired properties: 148c2ecf20Sopenharmony_ci - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci", 158c2ecf20Sopenharmony_ci soc-model is the name of SoC, such as mt8173, mt2712 etc, when using 168c2ecf20Sopenharmony_ci "mediatek,mtk-xhci" compatible string, you need SoC specific ones in 178c2ecf20Sopenharmony_ci addition, one of: 188c2ecf20Sopenharmony_ci - "mediatek,mt8173-xhci" 198c2ecf20Sopenharmony_ci - reg : specifies physical base address and size of the registers 208c2ecf20Sopenharmony_ci - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control 218c2ecf20Sopenharmony_ci - interrupts : interrupt used by the controller 228c2ecf20Sopenharmony_ci - power-domains : a phandle to USB power domain node to control USB's 238c2ecf20Sopenharmony_ci mtcmos 248c2ecf20Sopenharmony_ci - vusb33-supply : regulator of USB avdd3.3v 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci - clocks : a list of phandle + clock-specifier pairs, one for each 278c2ecf20Sopenharmony_ci entry in clock-names 288c2ecf20Sopenharmony_ci - clock-names : must contain 298c2ecf20Sopenharmony_ci "sys_ck": controller clock used by normal mode, 308c2ecf20Sopenharmony_ci the following ones are optional: 318c2ecf20Sopenharmony_ci "ref_ck": reference clock used by low power mode etc, 328c2ecf20Sopenharmony_ci "mcu_ck": mcu_bus clock for register access, 338c2ecf20Sopenharmony_ci "dma_ck": dma_bus clock for data transfer by DMA, 348c2ecf20Sopenharmony_ci "xhci_ck": controller clock 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ci - phys : see usb-hcd.yaml in the current directory 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ciOptional properties: 398c2ecf20Sopenharmony_ci - wakeup-source : enable USB remote wakeup; 408c2ecf20Sopenharmony_ci - mediatek,syscon-wakeup : phandle to syscon used to access the register 418c2ecf20Sopenharmony_ci of the USB wakeup glue layer between xHCI and SPM; it depends on 428c2ecf20Sopenharmony_ci "wakeup-source", and has two arguments: 438c2ecf20Sopenharmony_ci - the first one : register base address of the glue layer in syscon; 448c2ecf20Sopenharmony_ci - the second one : hardware version of the glue layer 458c2ecf20Sopenharmony_ci - 1 : used by mt8173 etc 468c2ecf20Sopenharmony_ci - 2 : used by mt2712 etc 478c2ecf20Sopenharmony_ci - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, 488c2ecf20Sopenharmony_ci bit1 for u3port1, ... etc; 498c2ecf20Sopenharmony_ci - vbus-supply : reference to the VBUS regulator; 508c2ecf20Sopenharmony_ci - usb3-lpm-capable : supports USB3.0 LPM 518c2ecf20Sopenharmony_ci - pinctrl-names : a pinctrl state named "default" must be defined 528c2ecf20Sopenharmony_ci - pinctrl-0 : pin control group 538c2ecf20Sopenharmony_ci See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 548c2ecf20Sopenharmony_ci - imod-interval-ns: default interrupt moderation interval is 5000ns 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ciadditionally the properties from usb-hcd.yaml (in the current directory) are 578c2ecf20Sopenharmony_cisupported. 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ciExample: 608c2ecf20Sopenharmony_ciusb30: usb@11270000 { 618c2ecf20Sopenharmony_ci compatible = "mediatek,mt8173-xhci"; 628c2ecf20Sopenharmony_ci reg = <0 0x11270000 0 0x1000>, 638c2ecf20Sopenharmony_ci <0 0x11280700 0 0x0100>; 648c2ecf20Sopenharmony_ci reg-names = "mac", "ippc"; 658c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 668c2ecf20Sopenharmony_ci power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 678c2ecf20Sopenharmony_ci clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, 688c2ecf20Sopenharmony_ci <&pericfg CLK_PERI_USB0>, 698c2ecf20Sopenharmony_ci <&pericfg CLK_PERI_USB1>; 708c2ecf20Sopenharmony_ci clock-names = "sys_ck", "ref_ck"; 718c2ecf20Sopenharmony_ci phys = <&phy_port0 PHY_TYPE_USB3>, 728c2ecf20Sopenharmony_ci <&phy_port1 PHY_TYPE_USB2>; 738c2ecf20Sopenharmony_ci vusb33-supply = <&mt6397_vusb_reg>; 748c2ecf20Sopenharmony_ci vbus-supply = <&usb_p1_vbus>; 758c2ecf20Sopenharmony_ci usb3-lpm-capable; 768c2ecf20Sopenharmony_ci mediatek,syscon-wakeup = <&pericfg 0x400 1>; 778c2ecf20Sopenharmony_ci wakeup-source; 788c2ecf20Sopenharmony_ci imod-interval-ns = <10000>; 798c2ecf20Sopenharmony_ci}; 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_ci2nd: dual-role mode with xHCI driver 828c2ecf20Sopenharmony_ci------------------------------------------------------------------------ 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ciIn the case, xhci is added as subnode to mtu3. An example and the DT binding 858c2ecf20Sopenharmony_cidetails of mtu3 can be found in: 868c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/usb/mediatek,mtu3.txt 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ciRequired properties: 898c2ecf20Sopenharmony_ci - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci", 908c2ecf20Sopenharmony_ci soc-model is the name of SoC, such as mt8173, mt2712 etc, when using 918c2ecf20Sopenharmony_ci "mediatek,mtk-xhci" compatible string, you need SoC specific ones in 928c2ecf20Sopenharmony_ci addition, one of: 938c2ecf20Sopenharmony_ci - "mediatek,mt8173-xhci" 948c2ecf20Sopenharmony_ci - reg : specifies physical base address and size of the registers 958c2ecf20Sopenharmony_ci - reg-names: should be "mac" for xHCI MAC 968c2ecf20Sopenharmony_ci - interrupts : interrupt used by the host controller 978c2ecf20Sopenharmony_ci - power-domains : a phandle to USB power domain node to control USB's 988c2ecf20Sopenharmony_ci mtcmos 998c2ecf20Sopenharmony_ci - vusb33-supply : regulator of USB avdd3.3v 1008c2ecf20Sopenharmony_ci 1018c2ecf20Sopenharmony_ci - clocks : a list of phandle + clock-specifier pairs, one for each 1028c2ecf20Sopenharmony_ci entry in clock-names 1038c2ecf20Sopenharmony_ci - clock-names : must contain "sys_ck", and the following ones are optional: 1048c2ecf20Sopenharmony_ci "ref_ck", "mcu_ck" and "dma_ck", "xhci_ck" 1058c2ecf20Sopenharmony_ci 1068c2ecf20Sopenharmony_ciOptional properties: 1078c2ecf20Sopenharmony_ci - vbus-supply : reference to the VBUS regulator; 1088c2ecf20Sopenharmony_ci - usb3-lpm-capable : supports USB3.0 LPM 1098c2ecf20Sopenharmony_ci 1108c2ecf20Sopenharmony_ciExample: 1118c2ecf20Sopenharmony_ciusb30: usb@11270000 { 1128c2ecf20Sopenharmony_ci compatible = "mediatek,mt8173-xhci"; 1138c2ecf20Sopenharmony_ci reg = <0 0x11270000 0 0x1000>; 1148c2ecf20Sopenharmony_ci reg-names = "mac"; 1158c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 1168c2ecf20Sopenharmony_ci power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 1178c2ecf20Sopenharmony_ci clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 1188c2ecf20Sopenharmony_ci clock-names = "sys_ck", "ref_ck"; 1198c2ecf20Sopenharmony_ci vusb33-supply = <&mt6397_vusb_reg>; 1208c2ecf20Sopenharmony_ci usb3-lpm-capable; 1218c2ecf20Sopenharmony_ci}; 122