18c2ecf20Sopenharmony_ci* NXP LPC32xx SoC USB Device Controller (UDC) 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible: Must be "nxp,lpc3220-udc" 58c2ecf20Sopenharmony_ci- reg: Physical base address of the controller and length of memory mapped 68c2ecf20Sopenharmony_ci region. 78c2ecf20Sopenharmony_ci- interrupts: The USB interrupts: 88c2ecf20Sopenharmony_ci * USB Device Low Priority Interrupt 98c2ecf20Sopenharmony_ci * USB Device High Priority Interrupt 108c2ecf20Sopenharmony_ci * USB Device DMA Interrupt 118c2ecf20Sopenharmony_ci * External USB Transceiver Interrupt (OTG ATX) 128c2ecf20Sopenharmony_ci- transceiver: phandle of the associated ISP1301 device - this is necessary for 138c2ecf20Sopenharmony_ci the UDC controller for connecting to the USB physical layer 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci isp1301: usb-transceiver@2c { 188c2ecf20Sopenharmony_ci compatible = "nxp,isp1301"; 198c2ecf20Sopenharmony_ci reg = <0x2c>; 208c2ecf20Sopenharmony_ci }; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci usbd@31020000 { 238c2ecf20Sopenharmony_ci compatible = "nxp,lpc3220-udc"; 248c2ecf20Sopenharmony_ci reg = <0x31020000 0x300>; 258c2ecf20Sopenharmony_ci interrupt-parent = <&mic>; 268c2ecf20Sopenharmony_ci interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; 278c2ecf20Sopenharmony_ci transceiver = <&isp1301>; 288c2ecf20Sopenharmony_ci }; 29