18c2ecf20Sopenharmony_ciHiSilicon STB xHCI
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThe device node for HiSilicon STB xHCI host controller
48c2ecf20Sopenharmony_ci
58c2ecf20Sopenharmony_ciRequired properties:
68c2ecf20Sopenharmony_ci - compatible: should be "hisilicon,hi3798cv200-xhci"
78c2ecf20Sopenharmony_ci - reg: specifies physical base address and size of the registers
88c2ecf20Sopenharmony_ci - interrupts : interrupt used by the controller
98c2ecf20Sopenharmony_ci - clocks: a list of phandle + clock-specifier pairs, one for each
108c2ecf20Sopenharmony_ci	entry in clock-names
118c2ecf20Sopenharmony_ci - clock-names: must contain
128c2ecf20Sopenharmony_ci	"bus": for bus clock
138c2ecf20Sopenharmony_ci	"utmi": for utmi clock
148c2ecf20Sopenharmony_ci	"pipe": for pipe clock
158c2ecf20Sopenharmony_ci	"suspend": for suspend clock
168c2ecf20Sopenharmony_ci - resets: a list of phandle and reset specifier pairs as listed in
178c2ecf20Sopenharmony_ci	reset-names property.
188c2ecf20Sopenharmony_ci - reset-names: must contain
198c2ecf20Sopenharmony_ci	"soft": for soft reset
208c2ecf20Sopenharmony_ci - phys: a list of phandle + phy specifier pairs
218c2ecf20Sopenharmony_ci - phy-names: must contain at least one of following:
228c2ecf20Sopenharmony_ci	"inno": for inno phy
238c2ecf20Sopenharmony_ci	"combo": for combo phy
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ciOptional properties:
268c2ecf20Sopenharmony_ci  - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
278c2ecf20Sopenharmony_ci  - usb3-lpm-capable: determines if platform is USB3 LPM capable
288c2ecf20Sopenharmony_ci  - imod-interval-ns: default interrupt moderation interval is 40000ns
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_ciExample:
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_cixhci0: xchi@f98a0000 {
338c2ecf20Sopenharmony_ci	compatible = "hisilicon,hi3798cv200-xhci";
348c2ecf20Sopenharmony_ci	reg = <0xf98a0000 0x10000>;
358c2ecf20Sopenharmony_ci	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
368c2ecf20Sopenharmony_ci	clocks = <&crg HISTB_USB3_BUS_CLK>,
378c2ecf20Sopenharmony_ci		 <&crg HISTB_USB3_UTMI_CLK>,
388c2ecf20Sopenharmony_ci		 <&crg HISTB_USB3_PIPE_CLK>,
398c2ecf20Sopenharmony_ci		 <&crg HISTB_USB3_SUSPEND_CLK>;
408c2ecf20Sopenharmony_ci	clock-names = "bus", "utmi", "pipe", "suspend";
418c2ecf20Sopenharmony_ci	resets = <&crg 0xb0 12>;
428c2ecf20Sopenharmony_ci	reset-names = "soft";
438c2ecf20Sopenharmony_ci	phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>;
448c2ecf20Sopenharmony_ci	phy-names = "inno", "combo";
458c2ecf20Sopenharmony_ci};
46