18c2ecf20Sopenharmony_ciST DWC3 glue logic
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciThis file documents the parameters for the dwc3-st driver.
48c2ecf20Sopenharmony_ciThis driver controls the glue logic used to configure the dwc3 core on
58c2ecf20Sopenharmony_ciSTiH407 based platforms.
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ciRequired properties:
88c2ecf20Sopenharmony_ci - compatible	: must be "st,stih407-dwc3"
98c2ecf20Sopenharmony_ci - reg		: glue logic base address and USB syscfg ctrl register offset
108c2ecf20Sopenharmony_ci - reg-names	: should be "reg-glue" and "syscfg-reg"
118c2ecf20Sopenharmony_ci - st,syscon	: should be phandle to system configuration node which
128c2ecf20Sopenharmony_ci		  encompasses the glue registers
138c2ecf20Sopenharmony_ci - resets	: list of phandle and reset specifier pairs. There should be two entries, one
148c2ecf20Sopenharmony_ci		  for the powerdown and softreset lines of the usb3 IP
158c2ecf20Sopenharmony_ci - reset-names	: list of reset signal names. Names should be "powerdown" and "softreset"
168c2ecf20Sopenharmony_ciSee: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
178c2ecf20Sopenharmony_ciSee: Documentation/devicetree/bindings/reset/reset.txt
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci - #address-cells, #size-cells : should be '1' if the device has sub-nodes
208c2ecf20Sopenharmony_ci   with 'reg' property
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci - pinctl-names	: A pinctrl state named "default" must be defined
238c2ecf20Sopenharmony_ciSee: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_ci - pinctrl-0	: Pin control group
268c2ecf20Sopenharmony_ciSee: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci - ranges	: allows valid 1:1 translation between child's address space and
298c2ecf20Sopenharmony_ci		  parent's address space
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ciSub-nodes:
328c2ecf20Sopenharmony_ciThe dwc3 core should be added as subnode to ST DWC3 glue as shown in the
338c2ecf20Sopenharmony_ciexample below. The DT binding details of dwc3 can be found in:
348c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/usb/dwc3.txt
358c2ecf20Sopenharmony_ci
368c2ecf20Sopenharmony_ciNB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
378c2ecf20Sopenharmony_ciis "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
388c2ecf20Sopenharmony_cior "device".
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ci[1] Documentation/devicetree/bindings/usb/generic.txt
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ciExample:
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_cist_dwc3: dwc3@8f94000 {
458c2ecf20Sopenharmony_ci	compatible	= "st,stih407-dwc3";
468c2ecf20Sopenharmony_ci	reg		= <0x08f94000 0x1000>, <0x110 0x4>;
478c2ecf20Sopenharmony_ci	reg-names	= "reg-glue", "syscfg-reg";
488c2ecf20Sopenharmony_ci	st,syscfg	= <&syscfg_core>;
498c2ecf20Sopenharmony_ci	resets		= <&powerdown STIH407_USB3_POWERDOWN>,
508c2ecf20Sopenharmony_ci			  <&softreset STIH407_MIPHY2_SOFTRESET>;
518c2ecf20Sopenharmony_ci	reset-names	= "powerdown", "softreset";
528c2ecf20Sopenharmony_ci	#address-cells	= <1>;
538c2ecf20Sopenharmony_ci	#size-cells	= <1>;
548c2ecf20Sopenharmony_ci	pinctrl-names	= "default";
558c2ecf20Sopenharmony_ci	pinctrl-0	= <&pinctrl_usb3>;
568c2ecf20Sopenharmony_ci	ranges;
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci	dwc3: dwc3@9900000 {
598c2ecf20Sopenharmony_ci		compatible	= "snps,dwc3";
608c2ecf20Sopenharmony_ci		reg		= <0x09900000 0x100000>;
618c2ecf20Sopenharmony_ci		interrupts	= <GIC_SPI 155 IRQ_TYPE_NONE>;
628c2ecf20Sopenharmony_ci		dr_mode		= "host";
638c2ecf20Sopenharmony_ci		phy-names	= "usb2-phy", "usb3-phy";
648c2ecf20Sopenharmony_ci		phys		= <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;
658c2ecf20Sopenharmony_ci	};
668c2ecf20Sopenharmony_ci};
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