18c2ecf20Sopenharmony_ciCavium SuperSpeed DWC3 USB SoC controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible: Should contain "cavium,octeon-7130-usb-uctl" 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired child node: 78c2ecf20Sopenharmony_ciA child node must exist to represent the core DWC3 IP block. The name of 88c2ecf20Sopenharmony_cithe node is not important. The content of the node is defined in dwc3.txt. 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ciExample device node: 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci uctl@1180069000000 { 138c2ecf20Sopenharmony_ci compatible = "cavium,octeon-7130-usb-uctl"; 148c2ecf20Sopenharmony_ci reg = <0x00011800 0x69000000 0x00000000 0x00000100>; 158c2ecf20Sopenharmony_ci ranges; 168c2ecf20Sopenharmony_ci #address-cells = <0x00000002>; 178c2ecf20Sopenharmony_ci #size-cells = <0x00000002>; 188c2ecf20Sopenharmony_ci refclk-frequency = <0x05f5e100>; 198c2ecf20Sopenharmony_ci refclk-type-ss = "dlmc_ref_clk0"; 208c2ecf20Sopenharmony_ci refclk-type-hs = "dlmc_ref_clk0"; 218c2ecf20Sopenharmony_ci power = <0x00000002 0x00000002 0x00000001>; 228c2ecf20Sopenharmony_ci xhci@1690000000000 { 238c2ecf20Sopenharmony_ci compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3"; 248c2ecf20Sopenharmony_ci reg = <0x00016900 0x00000000 0x00000010 0x00000000>; 258c2ecf20Sopenharmony_ci interrupt-parent = <0x00000010>; 268c2ecf20Sopenharmony_ci interrupts = <0x00000009 0x00000004>; 278c2ecf20Sopenharmony_ci }; 288c2ecf20Sopenharmony_ci }; 29