18c2ecf20Sopenharmony_ci* Universal Flash Storage (UFS) Host Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciUFSHC nodes are defined to describe on-chip UFS host controllers. 48c2ecf20Sopenharmony_ciEach UFS controller instance should have its own node. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0" 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci For Qualcomm SoCs must contain, as below, an 108c2ecf20Sopenharmony_ci SoC-specific compatible along with "qcom,ufshc" and 118c2ecf20Sopenharmony_ci the appropriate jedec string: 128c2ecf20Sopenharmony_ci "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 138c2ecf20Sopenharmony_ci "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 148c2ecf20Sopenharmony_ci "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 158c2ecf20Sopenharmony_ci "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 168c2ecf20Sopenharmony_ci "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 178c2ecf20Sopenharmony_ci- interrupts : <interrupt mapping for UFS host controller IRQ> 188c2ecf20Sopenharmony_ci- reg : <registers mapping> 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciOptional properties: 218c2ecf20Sopenharmony_ci- phys : phandle to UFS PHY node 228c2ecf20Sopenharmony_ci- phy-names : the string "ufsphy" when is found in a node, along 238c2ecf20Sopenharmony_ci with "phys" attribute, provides phandle to UFS PHY node 248c2ecf20Sopenharmony_ci- vdd-hba-supply : phandle to UFS host controller supply regulator node 258c2ecf20Sopenharmony_ci- vcc-supply : phandle to VCC supply regulator node 268c2ecf20Sopenharmony_ci- vccq-supply : phandle to VCCQ supply regulator node 278c2ecf20Sopenharmony_ci- vccq2-supply : phandle to VCCQ2 supply regulator node 288c2ecf20Sopenharmony_ci- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V 298c2ecf20Sopenharmony_ci or 2.7-3.6V. This boolean property when set, specifies 308c2ecf20Sopenharmony_ci to use low voltage range of 1.7-1.95V. Note for external 318c2ecf20Sopenharmony_ci UFS cards this property is invalid and valid VCC range is 328c2ecf20Sopenharmony_ci always 2.7-3.6V. 338c2ecf20Sopenharmony_ci- vcc-max-microamp : specifies max. load that can be drawn from vcc supply 348c2ecf20Sopenharmony_ci- vccq-max-microamp : specifies max. load that can be drawn from vccq supply 358c2ecf20Sopenharmony_ci- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci- clocks : List of phandle and clock specifier pairs 388c2ecf20Sopenharmony_ci- clock-names : List of clock input name strings sorted in the same 398c2ecf20Sopenharmony_ci order as the clocks property. 408c2ecf20Sopenharmony_ci "ref_clk" indicates reference clock frequency. 418c2ecf20Sopenharmony_ci UFS host supplies reference clock to UFS device and UFS device 428c2ecf20Sopenharmony_ci specification allows host to provide one of the 4 frequencies (19.2 MHz, 438c2ecf20Sopenharmony_ci 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is 448c2ecf20Sopenharmony_ci parsed and used to update the reference clock setting in device. 458c2ecf20Sopenharmony_ci Defaults to 26 MHz(as per specification) if not specified by host. 468c2ecf20Sopenharmony_ci- freq-table-hz : Array of <min max> operating frequencies stored in the same 478c2ecf20Sopenharmony_ci order as the clocks property. If this property is not 488c2ecf20Sopenharmony_ci defined or a value in the array is "0" then it is assumed 498c2ecf20Sopenharmony_ci that the frequency is set by the parent clock or a 508c2ecf20Sopenharmony_ci fixed rate clock source. 518c2ecf20Sopenharmony_ci-lanes-per-direction : number of lanes available per direction - either 1 or 2. 528c2ecf20Sopenharmony_ci Note that it is assume same number of lanes is used both 538c2ecf20Sopenharmony_ci directions at once. If not specified, default is 2 lanes per direction. 548c2ecf20Sopenharmony_ci- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose 558c2ecf20Sopenharmony_ci PHY reset from the UFS controller. 568c2ecf20Sopenharmony_ci- resets : reset node register 578c2ecf20Sopenharmony_ci- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. 588c2ecf20Sopenharmony_ci- reset-gpios : A phandle and gpio specifier denoting the GPIO connected 598c2ecf20Sopenharmony_ci to the RESET pin of the UFS memory device. 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ciNote: If above properties are not defined it can be assumed that the supply 628c2ecf20Sopenharmony_ciregulators or clocks are always on. 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ciExample: 658c2ecf20Sopenharmony_ci ufshc@fc598000 { 668c2ecf20Sopenharmony_ci compatible = "jedec,ufs-1.1"; 678c2ecf20Sopenharmony_ci reg = <0xfc598000 0x800>; 688c2ecf20Sopenharmony_ci interrupts = <0 28 0>; 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci vdd-hba-supply = <&xxx_reg0>; 718c2ecf20Sopenharmony_ci vcc-supply = <&xxx_reg1>; 728c2ecf20Sopenharmony_ci vcc-supply-1p8; 738c2ecf20Sopenharmony_ci vccq-supply = <&xxx_reg2>; 748c2ecf20Sopenharmony_ci vccq2-supply = <&xxx_reg3>; 758c2ecf20Sopenharmony_ci vcc-max-microamp = 500000; 768c2ecf20Sopenharmony_ci vccq-max-microamp = 200000; 778c2ecf20Sopenharmony_ci vccq2-max-microamp = 200000; 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>; 808c2ecf20Sopenharmony_ci clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk"; 818c2ecf20Sopenharmony_ci freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>; 828c2ecf20Sopenharmony_ci resets = <&reset 0 1>; 838c2ecf20Sopenharmony_ci reset-names = "rst"; 848c2ecf20Sopenharmony_ci phys = <&ufsphy1>; 858c2ecf20Sopenharmony_ci phy-names = "ufsphy"; 868c2ecf20Sopenharmony_ci #reset-cells = <1>; 878c2ecf20Sopenharmony_ci }; 88