18c2ecf20Sopenharmony_ci* Cadence Universal Flash Storage (UFS) Controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciUFS nodes are defined to describe on-chip UFS host controllers. 48c2ecf20Sopenharmony_ciEach UFS controller instance should have its own node. 58c2ecf20Sopenharmony_ciPlease see the ufshcd-pltfrm.txt for a list of all available properties. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci- compatible : Compatible list, contains one of the following controllers: 98c2ecf20Sopenharmony_ci "cdns,ufshc" - Generic CDNS HCI, 108c2ecf20Sopenharmony_ci "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY 118c2ecf20Sopenharmony_ci complemented with the JEDEC version: 128c2ecf20Sopenharmony_ci "jedec,ufs-2.0" 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci- reg : Address and length of the UFS register set. 158c2ecf20Sopenharmony_ci- interrupts : One interrupt mapping. 168c2ecf20Sopenharmony_ci- freq-table-hz : Clock frequency table. 178c2ecf20Sopenharmony_ci See the ufshcd-pltfrm.txt for details. 188c2ecf20Sopenharmony_ci- clocks : List of phandle and clock specifier pairs. 198c2ecf20Sopenharmony_ci- clock-names : List of clock input name strings sorted in the same 208c2ecf20Sopenharmony_ci order as the clocks property. "core_clk" is mandatory. 218c2ecf20Sopenharmony_ci Depending on a type of a PHY, 228c2ecf20Sopenharmony_ci the "phy_clk" clock can also be added, if needed. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciExample: 258c2ecf20Sopenharmony_ci ufs@fd030000 { 268c2ecf20Sopenharmony_ci compatible = "cdns,ufshc", "jedec,ufs-2.0"; 278c2ecf20Sopenharmony_ci reg = <0xfd030000 0x10000>; 288c2ecf20Sopenharmony_ci interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 298c2ecf20Sopenharmony_ci freq-table-hz = <0 0>, <0 0>; 308c2ecf20Sopenharmony_ci clocks = <&ufs_core_clk>, <&ufs_phy_clk>; 318c2ecf20Sopenharmony_ci clock-names = "core_clk", "phy_clk"; 328c2ecf20Sopenharmony_ci }; 33