18c2ecf20Sopenharmony_ciTimer64 28c2ecf20Sopenharmony_ci------- 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ciThe timer64 node describes C6X event timers. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci- compatible: must be "ti,c64x+timer64" 98c2ecf20Sopenharmony_ci- reg: base address and size of register region 108c2ecf20Sopenharmony_ci- interrupts: interrupt id 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciOptional properties: 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciExample: 198c2ecf20Sopenharmony_ci timer0: timer@25e0000 { 208c2ecf20Sopenharmony_ci compatible = "ti,c64x+timer64"; 218c2ecf20Sopenharmony_ci ti,core-mask = < 0x01 >; 228c2ecf20Sopenharmony_ci reg = <0x25e0000 0x40>; 238c2ecf20Sopenharmony_ci interrupt-parent = <&megamod_pic>; 248c2ecf20Sopenharmony_ci interrupts = < 16 >; 258c2ecf20Sopenharmony_ci }; 26