18c2ecf20Sopenharmony_ciSynopsys ARC Local Timer with Interrupt Capabilities 28c2ecf20Sopenharmony_ci- Found on all ARC CPUs (ARC700/ARCHS) 38c2ecf20Sopenharmony_ci- Can be optionally programmed to interrupt on Limit 48c2ecf20Sopenharmony_ci- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically 58c2ecf20Sopenharmony_ci TIMER0 used as clockevent provider (true for all ARC cores) 68c2ecf20Sopenharmony_ci TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ciRequired properties: 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci- compatible : should be "snps,arc-timer" 118c2ecf20Sopenharmony_ci- interrupts : single Interrupt going into parent intc 128c2ecf20Sopenharmony_ci (16 for ARCHS cores, 3 for ARC700 cores) 138c2ecf20Sopenharmony_ci- clocks : phandle to the source clock 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci timer0 { 188c2ecf20Sopenharmony_ci compatible = "snps,arc-timer"; 198c2ecf20Sopenharmony_ci interrupts = <3>; 208c2ecf20Sopenharmony_ci interrupt-parent = <&core_intc>; 218c2ecf20Sopenharmony_ci clocks = <&core_clk>; 228c2ecf20Sopenharmony_ci }; 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci timer1 { 258c2ecf20Sopenharmony_ci compatible = "snps,arc-timer"; 268c2ecf20Sopenharmony_ci clocks = <&core_clk>; 278c2ecf20Sopenharmony_ci }; 28