18c2ecf20Sopenharmony_ciNVIDIA Tegra30 timer 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free 48c2ecf20Sopenharmony_cirunning counter, and 5 watchdog modules. The first two channels may also 58c2ecf20Sopenharmony_citrigger a legacy watchdog reset. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ciRequired properties: 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, 108c2ecf20Sopenharmony_ci must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where 118c2ecf20Sopenharmony_ci <chip> is tegra124 or tegra132. 128c2ecf20Sopenharmony_ci- reg : Specifies base physical address and size of the registers. 138c2ecf20Sopenharmony_ci- interrupts : A list of 6 interrupts; one per each of timer channels 1 148c2ecf20Sopenharmony_ci through 5, and one for the shared interrupt for the remaining channels. 158c2ecf20Sopenharmony_ci- clocks : Must contain one entry, for the module clock. 168c2ecf20Sopenharmony_ci See ../clocks/clock-bindings.txt for details. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_citimer { 198c2ecf20Sopenharmony_ci compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 208c2ecf20Sopenharmony_ci reg = <0x60005000 0x400>; 218c2ecf20Sopenharmony_ci interrupts = <0 0 0x04 228c2ecf20Sopenharmony_ci 0 1 0x04 238c2ecf20Sopenharmony_ci 0 41 0x04 248c2ecf20Sopenharmony_ci 0 42 0x04 258c2ecf20Sopenharmony_ci 0 121 0x04 268c2ecf20Sopenharmony_ci 0 122 0x04>; 278c2ecf20Sopenharmony_ci clocks = <&tegra_car 214>; 288c2ecf20Sopenharmony_ci}; 29