18c2ecf20Sopenharmony_ciZTE ZX296702 SPDIF controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci - compatible : Must be "zte,zx296702-spdif" 58c2ecf20Sopenharmony_ci - reg : Must contain SPDIF core's registers location and length 68c2ecf20Sopenharmony_ci - clocks : Pairs of phandle and specifier referencing the controller's clocks. 78c2ecf20Sopenharmony_ci - clock-names: "tx" for the clock to the SPDIF interface. 88c2ecf20Sopenharmony_ci - dmas: Pairs of phandle and specifier for the DMA channel that is used by 98c2ecf20Sopenharmony_ci the core. The core expects one dma channel for transmit. 108c2ecf20Sopenharmony_ci - dma-names : Must be "tx" 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciFor more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties 138c2ecf20Sopenharmony_ciplease check: 148c2ecf20Sopenharmony_ci * resource-names.txt 158c2ecf20Sopenharmony_ci * clock/clock-bindings.txt 168c2ecf20Sopenharmony_ci * dma/dma.txt 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciExample: 198c2ecf20Sopenharmony_ci spdif0: spdif0@b004000 { 208c2ecf20Sopenharmony_ci compatible = "zte,zx296702-spdif"; 218c2ecf20Sopenharmony_ci reg = <0x0b004000 0x1000>; 228c2ecf20Sopenharmony_ci clocks = <&lsp0clk ZX296702_SPDIF0_DIV>; 238c2ecf20Sopenharmony_ci clock-names = "tx"; 248c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 258c2ecf20Sopenharmony_ci dmas = <&dma 4>; 268c2ecf20Sopenharmony_ci dma-names = "tx"; 278c2ecf20Sopenharmony_ci }; 28