18c2ecf20Sopenharmony_ciDevice-Tree bindings for Xilinx SPDIF IP 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe IP supports playback and capture of SPDIF audio 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciRequired properties: 68c2ecf20Sopenharmony_ci - compatible: "xlnx,spdif-2.0" 78c2ecf20Sopenharmony_ci - clock-names: List of input clocks. 88c2ecf20Sopenharmony_ci Required elements: "s_axi_aclk", "aud_clk_i" 98c2ecf20Sopenharmony_ci - clocks: Input clock specifier. Refer to common clock bindings. 108c2ecf20Sopenharmony_ci - reg: Base address and address length of the IP core instance. 118c2ecf20Sopenharmony_ci - interrupts-parent: Phandle for interrupt controller. 128c2ecf20Sopenharmony_ci - interrupts: List of Interrupt numbers. 138c2ecf20Sopenharmony_ci - xlnx,spdif-mode: 0 :- receiver mode 148c2ecf20Sopenharmony_ci 1 :- transmitter mode 158c2ecf20Sopenharmony_ci - xlnx,aud_clk_i: input audio clock value. 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciExample: 188c2ecf20Sopenharmony_ci spdif_0: spdif@80010000 { 198c2ecf20Sopenharmony_ci clock-names = "aud_clk_i", "s_axi_aclk"; 208c2ecf20Sopenharmony_ci clocks = <&misc_clk_0>, <&clk 71>; 218c2ecf20Sopenharmony_ci compatible = "xlnx,spdif-2.0"; 228c2ecf20Sopenharmony_ci interrupt-names = "spdif_interrupt"; 238c2ecf20Sopenharmony_ci interrupt-parent = <&gic>; 248c2ecf20Sopenharmony_ci interrupts = <0 91 4>; 258c2ecf20Sopenharmony_ci reg = <0x0 0x80010000 0x0 0x10000>; 268c2ecf20Sopenharmony_ci xlnx,spdif-mode = <1>; 278c2ecf20Sopenharmony_ci xlnx,aud_clk_i = <49152913>; 288c2ecf20Sopenharmony_ci }; 29