18c2ecf20Sopenharmony_ciDevice-Tree bindings for Xilinx PL audio formatter 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe IP core supports DMA, data formatting(AES<->PCM conversion) 48c2ecf20Sopenharmony_ciof audio samples. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci - compatible: "xlnx,audio-formatter-1.0" 88c2ecf20Sopenharmony_ci - interrupt-names: Names specified to list of interrupts in same 98c2ecf20Sopenharmony_ci order mentioned under "interrupts". 108c2ecf20Sopenharmony_ci List of supported interrupt names are: 118c2ecf20Sopenharmony_ci "irq_mm2s" : interrupt from MM2S block 128c2ecf20Sopenharmony_ci "irq_s2mm" : interrupt from S2MM block 138c2ecf20Sopenharmony_ci - interrupts-parent: Phandle for interrupt controller. 148c2ecf20Sopenharmony_ci - interrupts: List of Interrupt numbers. 158c2ecf20Sopenharmony_ci - reg: Base address and size of the IP core instance. 168c2ecf20Sopenharmony_ci - clock-names: List of input clocks. 178c2ecf20Sopenharmony_ci Required elements: "s_axi_lite_aclk", "aud_mclk" 188c2ecf20Sopenharmony_ci - clocks: Input clock specifier. Refer to common clock bindings. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ciExample: 218c2ecf20Sopenharmony_ci audio_ss_0_audio_formatter_0: audio_formatter@80010000 { 228c2ecf20Sopenharmony_ci compatible = "xlnx,audio-formatter-1.0"; 238c2ecf20Sopenharmony_ci interrupt-names = "irq_mm2s", "irq_s2mm"; 248c2ecf20Sopenharmony_ci interrupt-parent = <&gic>; 258c2ecf20Sopenharmony_ci interrupts = <0 104 4>, <0 105 4>; 268c2ecf20Sopenharmony_ci reg = <0x0 0x80010000 0x0 0x1000>; 278c2ecf20Sopenharmony_ci clock-names = "s_axi_lite_aclk", "aud_mclk"; 288c2ecf20Sopenharmony_ci clocks = <&clk 71>, <&clk_wiz_1 0>; 298c2ecf20Sopenharmony_ci }; 30