18c2ecf20Sopenharmony_ciRT5514 audio CODEC 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis device supports both I2C and SPI. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciRequired properties: 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci- compatible : "realtek,rt5514". 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci- reg : the I2C address of the device for I2C, the chip select 108c2ecf20Sopenharmony_ci number for SPI. 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciOptional properties: 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci- clocks: The phandle of the master clock to the CODEC 158c2ecf20Sopenharmony_ci- clock-names: Should be "mclk" 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci- interrupts: The interrupt number to the cpu. The interrupt specifier format 188c2ecf20Sopenharmony_ci depends on the interrupt controller. 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci- realtek,dmic-init-delay-ms 218c2ecf20Sopenharmony_ci Set the DMIC initial delay (ms) to wait it ready for I2C. 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ciPins on the device (for linking into audio routes) for I2C: 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci * DMIC1L 268c2ecf20Sopenharmony_ci * DMIC1R 278c2ecf20Sopenharmony_ci * DMIC2L 288c2ecf20Sopenharmony_ci * DMIC2R 298c2ecf20Sopenharmony_ci * AMICL 308c2ecf20Sopenharmony_ci * AMICR 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ciExample: 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_cirt5514: codec@57 { 358c2ecf20Sopenharmony_ci compatible = "realtek,rt5514"; 368c2ecf20Sopenharmony_ci reg = <0x57>; 378c2ecf20Sopenharmony_ci}; 38