18c2ecf20Sopenharmony_ciNVIDIA Tegra30 I2S controller 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124, 58c2ecf20Sopenharmony_ci must contain "nvidia,tegra124-i2s". Otherwise, must contain 68c2ecf20Sopenharmony_ci "nvidia,<chip>-i2s" plus at least one of the above, where <chip> is 78c2ecf20Sopenharmony_ci tegra114 or tegra132. 88c2ecf20Sopenharmony_ci- reg : Should contain I2S registers location and length 98c2ecf20Sopenharmony_ci- clocks : Must contain one entry, for the module clock. 108c2ecf20Sopenharmony_ci See ../clocks/clock-bindings.txt for details. 118c2ecf20Sopenharmony_ci- resets : Must contain an entry for each entry in reset-names. 128c2ecf20Sopenharmony_ci See ../reset/reset.txt for details. 138c2ecf20Sopenharmony_ci- reset-names : Must include the following entries: 148c2ecf20Sopenharmony_ci - i2s 158c2ecf20Sopenharmony_ci- nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) 168c2ecf20Sopenharmony_ci first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ciExample: 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_cii2s@70080300 { 218c2ecf20Sopenharmony_ci compatible = "nvidia,tegra30-i2s"; 228c2ecf20Sopenharmony_ci reg = <0x70080300 0x100>; 238c2ecf20Sopenharmony_ci nvidia,ahub-cif-ids = <4 4>; 248c2ecf20Sopenharmony_ci clocks = <&tegra_car 11>; 258c2ecf20Sopenharmony_ci resets = <&tegra_car 11>; 268c2ecf20Sopenharmony_ci reset-names = "i2s"; 278c2ecf20Sopenharmony_ci}; 28