18c2ecf20Sopenharmony_ciMediatek ALSA BT SCO CVSD/MSBC Driver 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciRequired properties: 48c2ecf20Sopenharmony_ci- compatible = "mediatek,mtk-btcvsd-snd"; 58c2ecf20Sopenharmony_ci- reg: register location and size of PKV and SRAM_BANK2 68c2ecf20Sopenharmony_ci- interrupts: should contain BTSCO interrupt 78c2ecf20Sopenharmony_ci- mediatek,infracfg: the phandles of INFRASYS 88c2ecf20Sopenharmony_ci- mediatek,offset: Array contains of register offset and mask 98c2ecf20Sopenharmony_ci infra_misc_offset, 108c2ecf20Sopenharmony_ci infra_conn_bt_cvsd_mask, 118c2ecf20Sopenharmony_ci cvsd_mcu_read_offset, 128c2ecf20Sopenharmony_ci cvsd_mcu_write_offset, 138c2ecf20Sopenharmony_ci cvsd_packet_indicator_offset 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciExample: 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci mtk-btcvsd-snd@18000000 { 188c2ecf20Sopenharmony_ci compatible = "mediatek,mtk-btcvsd-snd"; 198c2ecf20Sopenharmony_ci reg=<0 0x18000000 0 0x1000>, 208c2ecf20Sopenharmony_ci <0 0x18080000 0 0x8000>; 218c2ecf20Sopenharmony_ci interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 228c2ecf20Sopenharmony_ci mediatek,infracfg = <&infrasys>; 238c2ecf20Sopenharmony_ci mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; 248c2ecf20Sopenharmony_ci }; 25