18c2ecf20Sopenharmony_ciFreescale Synchronous Serial Interface 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThe SSI is a serial device that communicates with audio codecs. It can 48c2ecf20Sopenharmony_cibe programmed in AC97, I2S, left-justified, or right-justified modes. 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciRequired properties: 78c2ecf20Sopenharmony_ci- compatible: Compatible list, should contain one of the following 88c2ecf20Sopenharmony_ci compatibles: 98c2ecf20Sopenharmony_ci fsl,mpc8610-ssi 108c2ecf20Sopenharmony_ci fsl,imx51-ssi 118c2ecf20Sopenharmony_ci fsl,imx35-ssi 128c2ecf20Sopenharmony_ci fsl,imx21-ssi 138c2ecf20Sopenharmony_ci- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on. 148c2ecf20Sopenharmony_ci- reg: Offset and length of the register set for the device. 158c2ecf20Sopenharmony_ci- interrupts: <a b> where a is the interrupt number and b is a 168c2ecf20Sopenharmony_ci field that represents an encoding of the sense and 178c2ecf20Sopenharmony_ci level information for the interrupt. This should be 188c2ecf20Sopenharmony_ci encoded based on the information in section 2) 198c2ecf20Sopenharmony_ci depending on the type of interrupt controller you 208c2ecf20Sopenharmony_ci have. 218c2ecf20Sopenharmony_ci- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. 228c2ecf20Sopenharmony_ci This number is the maximum allowed value for SFCSR[TFWM0]. 238c2ecf20Sopenharmony_ci - clocks: "ipg" - Required clock for the SSI unit 248c2ecf20Sopenharmony_ci "baud" - Required clock for SSI master mode. Otherwise this 258c2ecf20Sopenharmony_ci clock is not used 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciRequired are also ac97 link bindings if ac97 is used. See 288c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary 298c2ecf20Sopenharmony_cibindings. 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ciOptional properties: 328c2ecf20Sopenharmony_ci- codec-handle: Phandle to a 'codec' node that defines an audio 338c2ecf20Sopenharmony_ci codec connected to this SSI. This node is typically 348c2ecf20Sopenharmony_ci a child of an I2C or other control node. 358c2ecf20Sopenharmony_ci- fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to 368c2ecf20Sopenharmony_ci filter the codec stream. This is necessary for some boards 378c2ecf20Sopenharmony_ci where an incompatible codec is connected to this SSI, e.g. 388c2ecf20Sopenharmony_ci on pca100 and pcm043. 398c2ecf20Sopenharmony_ci- dmas: Generic dma devicetree binding as described in 408c2ecf20Sopenharmony_ci Documentation/devicetree/bindings/dma/dma.txt. 418c2ecf20Sopenharmony_ci- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq 428c2ecf20Sopenharmony_ci is not defined. 438c2ecf20Sopenharmony_ci- fsl,mode: The operating mode for the AC97 interface only. 448c2ecf20Sopenharmony_ci "ac97-slave" - AC97 mode, SSI is clock slave 458c2ecf20Sopenharmony_ci "ac97-master" - AC97 mode, SSI is clock master 468c2ecf20Sopenharmony_ci- fsl,ssi-asynchronous: 478c2ecf20Sopenharmony_ci If specified, the SSI is to be programmed in asynchronous 488c2ecf20Sopenharmony_ci mode. In this mode, pins SRCK, STCK, SRFS, and STFS must 498c2ecf20Sopenharmony_ci all be connected to valid signals. In synchronous mode, 508c2ecf20Sopenharmony_ci SRCK and SRFS are ignored. Asynchronous mode allows 518c2ecf20Sopenharmony_ci playback and capture to use different sample sizes and 528c2ecf20Sopenharmony_ci sample rates. Some drivers may require that SRCK and STCK 538c2ecf20Sopenharmony_ci be connected together, and SRFS and STFS be connected 548c2ecf20Sopenharmony_ci together. This would still allow different sample sizes, 558c2ecf20Sopenharmony_ci but not different sample rates. 568c2ecf20Sopenharmony_ci- fsl,playback-dma: Phandle to a node for the DMA channel to use for 578c2ecf20Sopenharmony_ci playback of audio. This is typically dictated by SOC 588c2ecf20Sopenharmony_ci design. See the notes below. 598c2ecf20Sopenharmony_ci Only used on Power Architecture. 608c2ecf20Sopenharmony_ci- fsl,capture-dma: Phandle to a node for the DMA channel to use for 618c2ecf20Sopenharmony_ci capture (recording) of audio. This is typically dictated 628c2ecf20Sopenharmony_ci by SOC design. See the notes below. 638c2ecf20Sopenharmony_ci Only used on Power Architecture. 648c2ecf20Sopenharmony_ci 658c2ecf20Sopenharmony_ciChild 'codec' node required properties: 668c2ecf20Sopenharmony_ci- compatible: Compatible list, contains the name of the codec 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ciChild 'codec' node optional properties: 698c2ecf20Sopenharmony_ci- clock-frequency: The frequency of the input clock, which typically comes 708c2ecf20Sopenharmony_ci from an on-board dedicated oscillator. 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ciNotes on fsl,playback-dma and fsl,capture-dma: 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ciOn SOCs that have an SSI, specific DMA channels are hard-wired for playback 758c2ecf20Sopenharmony_ciand capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for 768c2ecf20Sopenharmony_ciplayback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for 778c2ecf20Sopenharmony_ciplayback and DMA channel 3 for capture. The developer can choose which 788c2ecf20Sopenharmony_ciDMA controller to use, but the channels themselves are hard-wired. The 798c2ecf20Sopenharmony_cipurpose of these two properties is to represent this hardware design. 808c2ecf20Sopenharmony_ci 818c2ecf20Sopenharmony_ciThe device tree nodes for the DMA channels that are referenced by 828c2ecf20Sopenharmony_ci"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with 838c2ecf20Sopenharmony_ci"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g. 848c2ecf20Sopenharmony_ci"fsl,mpc8610-dma-channel") can remain. If these nodes are left as 858c2ecf20Sopenharmony_ci"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA 868c2ecf20Sopenharmony_cidrivers (fsldma) will attempt to use them, and it will conflict with the 878c2ecf20Sopenharmony_cisound drivers. 88