18c2ecf20Sopenharmony_ciCirrus Logic CS4271 DT bindings 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ciThis driver supports both the I2C and the SPI bus. 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ciRequired properties: 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci - compatible: "cirrus,cs4271" 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciFor required properties on SPI, please consult 108c2ecf20Sopenharmony_ciDocumentation/devicetree/bindings/spi/spi-bus.txt 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ciRequired properties on I2C: 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci - reg: the i2c address 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ciOptional properties: 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci - reset-gpio: a GPIO spec to define which pin is connected to the chip's 208c2ecf20Sopenharmony_ci !RESET pin 218c2ecf20Sopenharmony_ci - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag 228c2ecf20Sopenharmony_ci is enabled. 238c2ecf20Sopenharmony_ci - cirrus,enable-soft-reset: 248c2ecf20Sopenharmony_ci The CS4271 requires its LRCLK and MCLK to be stable before its RESET 258c2ecf20Sopenharmony_ci line is de-asserted. That also means that clocks cannot be changed 268c2ecf20Sopenharmony_ci without putting the chip back into hardware reset, which also requires 278c2ecf20Sopenharmony_ci a complete re-initialization of all registers. 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci One (undocumented) workaround is to assert and de-assert the PDN bit 308c2ecf20Sopenharmony_ci in the MODE2 register. This workaround can be enabled with this DT 318c2ecf20Sopenharmony_ci property. 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci Note that this is not needed in case the clocks are stable 348c2ecf20Sopenharmony_ci throughout the entire runtime of the codec. 358c2ecf20Sopenharmony_ci 368c2ecf20Sopenharmony_ci - vd-supply: Digital power 378c2ecf20Sopenharmony_ci - vl-supply: Logic power 388c2ecf20Sopenharmony_ci - va-supply: Analog Power 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_ciExamples: 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci codec_i2c: cs4271@10 { 438c2ecf20Sopenharmony_ci compatible = "cirrus,cs4271"; 448c2ecf20Sopenharmony_ci reg = <0x10>; 458c2ecf20Sopenharmony_ci reset-gpio = <&gpio 23 0>; 468c2ecf20Sopenharmony_ci vd-supply = <&vdd_3v3_reg>; 478c2ecf20Sopenharmony_ci vl-supply = <&vdd_3v3_reg>; 488c2ecf20Sopenharmony_ci va-supply = <&vdd_3v3_reg>; 498c2ecf20Sopenharmony_ci }; 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci codec_spi: cs4271@0 { 528c2ecf20Sopenharmony_ci compatible = "cirrus,cs4271"; 538c2ecf20Sopenharmony_ci reg = <0x0>; 548c2ecf20Sopenharmony_ci reset-gpio = <&gpio 23 0>; 558c2ecf20Sopenharmony_ci spi-max-frequency = <6000000>; 568c2ecf20Sopenharmony_ci }; 578c2ecf20Sopenharmony_ci 58