18c2ecf20Sopenharmony_ciBindings for I2S controller built into xtfpga Xtensa bitstreams.
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible: shall be "cdns,xtfpga-i2s".
58c2ecf20Sopenharmony_ci- reg: memory region (address and length) with device registers.
68c2ecf20Sopenharmony_ci- interrupts: interrupt for the device.
78c2ecf20Sopenharmony_ci- clocks: phandle to the clk used as master clock. I2S bus clock
88c2ecf20Sopenharmony_ci  is derived from it.
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ciExamples:
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci	i2s0: xtfpga-i2s@d080000 {
138c2ecf20Sopenharmony_ci		#sound-dai-cells = <0>;
148c2ecf20Sopenharmony_ci		compatible = "cdns,xtfpga-i2s";
158c2ecf20Sopenharmony_ci		reg = <0x0d080000 0x40>;
168c2ecf20Sopenharmony_ci		interrupts = <2 1>;
178c2ecf20Sopenharmony_ci		clocks = <&cdce706 4>;
188c2ecf20Sopenharmony_ci	};
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