18c2ecf20Sopenharmony_ciBroadcom DSL/PON BCM63xx Audio I2S controller
28c2ecf20Sopenharmony_ci
38c2ecf20Sopenharmony_ciRequired properties:
48c2ecf20Sopenharmony_ci- compatible:     Should be "brcm,bcm63xx-i2s".
58c2ecf20Sopenharmony_ci- #address-cells: 32bit valued, 1 cell.
68c2ecf20Sopenharmony_ci- #size-cells:    32bit valued, 0 cell.
78c2ecf20Sopenharmony_ci- reg:            Should contain audio registers location and length
88c2ecf20Sopenharmony_ci- interrupts:     Should contain the interrupt for the controller.
98c2ecf20Sopenharmony_ci- clocks:         Must contain an entry for each entry in clock-names.
108c2ecf20Sopenharmony_ci                  Please refer to clock-bindings.txt.
118c2ecf20Sopenharmony_ci- clock-names:    One of each entry matching the clocks phandles list:
128c2ecf20Sopenharmony_ci                  - "i2sclk" (generated clock) Required.
138c2ecf20Sopenharmony_ci                  - "i2sosc" (fixed 200MHz clock) Required.
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ci(1) : The generated clock is required only when any of TX and RX
168c2ecf20Sopenharmony_ci      works on Master Mode.
178c2ecf20Sopenharmony_ci(2) : The fixed 200MHz clock is from internal chip and always on
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ciExample:
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci		i2s: bcm63xx-i2s {
228c2ecf20Sopenharmony_ci			#address-cells = <1>;
238c2ecf20Sopenharmony_ci			#size-cells = <0>;
248c2ecf20Sopenharmony_ci			compatible = "brcm,bcm63xx-i2s";
258c2ecf20Sopenharmony_ci			reg = <0xFF802080 0xFF>;
268c2ecf20Sopenharmony_ci			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
278c2ecf20Sopenharmony_ci			clocks = <&i2sclk>, <&osc>;
288c2ecf20Sopenharmony_ci			clock-names = "i2sclk","i2sosc";
298c2ecf20Sopenharmony_ci		};
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